further JiffyDOS timing fixes

c64/kernal/iec_fast/iec_rx_byte_jiffydos.s

@@ -36,14 +36,15 @@ iec_rx_byte_jiffydos:
 	// Ask device to start sending bits
 	stx CIA2_PRA                       // cycles: 4
 
-	// XXX we have to wait 20 cycles??? seriously??? what the hell shall we do here???
-	pla // 4 cycles
-	pha // 3 cycles
-	pla // 4 cycles
-	pha // 3 cycles
-	nop // 2 cycles
-	nop // 2 cycles
-	nop // 2 cycles
+	// XXX how many cycles? (each NOP is 2)
+
+	nop
+	nop
+	nop
+
+	nop
+	nop
+	nop
 
 	// Get bits, cycles: 4 + 2 + 2 = 8
 	lda CIA2_PRA                       // bits 0 and 1 on CLK/DATA

c64/kernal/iec_fast/jiffydos_wait_line.s

@@ -10,9 +10,10 @@
 
 jiffydos_wait_line:
 
-	lda VIC_SCROLY
-	and #$10
-	beq jiffydos_wait_line_done        // screen is disabled, no need to watch for badlines
+	// One might try to optimize the code by checking for disabled screen
+	// (bit 4 of VIC_SCROLY); problem: VIC checks this bit only once per frame:
+	// - https://www.lemon64.com/forum/viewtopic.php?t=56582
+	// so it would complicated the code
 
 	// Avoid 2 lines before the badline, otherwise VIC will ruin the synchronization
 	lda VIC_RASTER