more work on CP/M memory banking

src/zvm_m65/,aliases_zvm.s

@@ -69,9 +69,7 @@
 ;
 
 !addr PTR_IXY_d              = $30               ; 4 bytes - calculated address IX+d / IY+d       XXX - review usage !!!
-!addr PTR_IXY_d_EXT1         = PTR_IXY_d+2
 !addr PTR_DATA               = $34               ; 4 bytes - calculated data source address       XXX - review usage !!! also check functions using ZVM_store_next
-!addr PTR_DATA_EXT1          = PTR_DATA+2
 !addr ADDR_IO                = $38               ; 4 bytes - address for fetching/storing the IO
 
 !addr REG_TMP1               = $3C               ; 1 byte  - emulation-specific temporary storage
@@ -80,17 +78,19 @@
 ;                              $3E               ; 2 bytes - reserved
 
 ;
-; Memory banking vectors
+; Memory banking vectors - every single routine destroys .Y in case of bank 0
 ;
 
+; XXX inline some of these routines - provide separate opcode implementations for various banks
+
 !addr zvm_bankvectors__start = $40
 
-!addr VEC_fetch_via_PC_inc   = $40               ; fetch to .A from (PC), increment PC afterwards      XXX consider providing dual-byte retrieval
+!addr VEC_fetch_via_PC_inc   = $40               ; fetch to .A from (PC), increment PC afterwards
+!addr VEC_fetch_stack        = $42               ; fetch to .A - stack POP operation, destroys .X
+!addr VEC_store_stack        = $44               ; store .A - stack PUSH operation, destroys .X
 
 ; XXX implement routines for vectors below
 
-!addr VEC_fetch_stack        = $42
-!addr VEC_store_stack        = $44
 !addr VEC_fetch_via_BC       = $46 
 !addr VEC_store_via_BC       = $48
 !addr VEC_fetch_via_DE       = $4A

src/zvm_m65/z80_reset.s

@@ -23,15 +23,25 @@ Z80_reset:
 	sta REG_R06
 
 	; The engine requires all the Z80 visible memory to be present within the 1st 16MB,
-	; so set the most significant buytes of 32-bit pointers to 0.
+	; so set the most significant bytes of 32-bit pointers to 0.
 
 	stz REG_BC_EXT1+1
 	stz REG_DE_EXT1+1
 	stz REG_HL_EXT1+1
 	stz REG_SP_EXT1+1
 	stz REG_PC_EXT1+1
-	stz PTR_IXY_d_EXT1+1
-	stz PTR_DATA_EXT1+1
+	stz PTR_IXY_d+3
+	stz PTR_DATA+3
+
+	; Some pointers are useful for bank 0 only - we can set another byte there
+
+	lda #$05
+	
+	sta REG_BC_EXT1+0
+	sta REG_DE_EXT1+0
+	sta REG_HL_EXT1+0
+	sta REG_SP_EXT1+0
+	sta REG_PC_EXT1+0
 
 	; Default bank is 1 (the fastest, continuous memory)	
 

src/zvm_m65/z80_table_gen.s

@@ -12,36 +12,61 @@ z80_table_gen:
 	;
 	; Generating:   z80_atable_mi_bank0, z80_atable_hi_bank0
 	; Dependencies: NONE
+	; Destroys:     NONE
 	;
 
 	ldx #$00
 	
 @loop_atable_bank0:
 	
-	cpx #$E0
-	bcs @common_addr
+	cpx #$C0
+	bcs @addr_common
 	
-	; Memory area $0000-$DFFF - maps to $02000-$0FFFF - 56KB
+	; Memory area $0000-$BFFF - maps somewhere to $0xxxx range - 48KB total
 
-	lda #$04
+	lda #$00
 	sta z80_atable_hi_bank0, x
+
 	txa
+	cmp #$60
+	bcc @addr_lo
+
+@addr_hi:
+
+	; Memory area $6000-$BFFF - maps to $0C000 - $0FFFF - 24 KB
+
 	clc
+	adc #$40
+
+@addr_lo:
+
+	; Memory area $0000-$5FFF - maps to $02000 - $07FFF - 24 KB
+
 	adc #$20
 	sta z80_atable_mi_bank0, x
 
-@common_addr:
+	bra @loop_atable_next
+
+@addr_common:
 	
-	; Memory area $E000-$FFFF - maps to $4E000-$4FFFF - 8KB
+	; Memory area $C000-$FFFF - maps to $5C000-$5FFFF - 16KB
 	
-	lda #$04
+	lda #$05
 	sta z80_atable_hi_bank0, x
 	txa
 	sta z80_atable_mi_bank0, x	
 	
+@loop_atable_next:
+
 	inx
 	bne @loop_atable_bank0
 
+	;
+	; Generating:   XXX
+	; Dependencies: NONE
+	; Destroys:     NONE
+	;
+
 	; XXX add more tables here
 
 	;

src/zvm_m65/zvm_banking.s

@@ -7,11 +7,17 @@
 ZVM_bank0_vectab:
 
 	!word ZVM_bank0_fetch_via_PC_inc
+	!word ZVM_bank0_fetch_stack
+	!word ZVM_bank0_store_stack
+
 	; XXX add remaining routines here
 
 ZVM_bank1_vectab:
 
 	!word ZVM_bank1_fetch_via_PC_inc
+	!word ZVM_bank1_fetch_stack
+	!word ZVM_bank1_store_stack
+
 	; XXX add remaining routines here
 
 ;
@@ -39,13 +45,8 @@ ZVM_set_bank_1:
 
 	lda #$05
 	
-	sta REG_BC_EXT1+0
-	sta REG_DE_EXT1+0
-	sta REG_HL_EXT1+0
-	sta REG_SP_EXT1+0
-	sta REG_PC_EXT1+0
-	sta PTR_IXY_d_EXT1+0
-	sta PTR_DATA_EXT1+0
+	sta PTR_IXY_d+2
+	sta PTR_DATA+2
 
 	rts
 
@@ -61,21 +62,64 @@ ZVM_bank0_fetch_via_PC_inc:
 	lda z80_atable_mi_bank0,y
 	sta PTR_DATA+1
 	lda z80_atable_hi_bank0,y
-	sta PTR_DATA+1
+	sta PTR_DATA+2
 	
 	lda [PTR_DATA], z
-
 	inw REG_PC
+
 	rts
 
 ZVM_bank1_fetch_via_PC_inc:
 
 	lda [REG_PC], z
-
 	inw REG_PC
+
 	rts
 
+ZVM_bank0_fetch_stack:
 
+	ldx REG_SP+0
+	stx PTR_DATA+0
+	ldy REG_SP+1
+	ldx z80_atable_mi_bank0,y
+	stx PTR_DATA+1
+	ldx z80_atable_hi_bank0,y
+	stx PTR_DATA+2
+	
+	lda [PTR_DATA], z
+	inw REG_SP
+
+	rts
+
+ZVM_bank1_fetch_stack:
+
+	lda [REG_SP], z
+	inw REG_SP
+
+	rts
+
+ZVM_bank0_store_stack:
+
+	dew REG_SP
+
+	ldx REG_SP+0
+	stx PTR_DATA+0
+	ldy REG_SP+1
+	ldx z80_atable_mi_bank0,y
+	stx PTR_DATA+1
+	ldx z80_atable_hi_bank0,y
+	stx PTR_DATA+2
+
+	sta [PTR_DATA], z
+
+	rts
+
+ZVM_bank1_store_stack:
+
+	dew REG_SP
+	sta [REG_SP], z
+
+	rts