handled all similarities >3, updated binaries

This commit is contained in:
FeralChild64 committed 2019-10-25 18:25:59 +02:00
1 parent a052b3e25c
commit 28d0fa5ecf
61 files changed
+164 -1

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@@ -31,7 +31,7 @@
// PETSCII codes for our extended screen editor XXX implement these
.const KEY_BOTTOM = $02 // CTRL+B - DolphinDOS compatible
.const KEY_BOTTOM = $02 // CTRL+B - Open ROMs unofficial, DolphinDOS compatible
.const KEY_TAB_FW = $8F // CTRL+>, TAB - Open ROMs unofficial, original TAB conflicts with C64 PETSCII
.const KEY_TAB_BW = $80 // CTRL+<, SHIFT+TAB - Open ROMs unofficial, original TAB conflicts with C64 PETSCII
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$00 + STA $0291
Instruction (storing data in a documented location) and a part. Not copyrightable.
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$00 + STA $0200,X
Instruction (storing data in a documented location) and a part. Not copyrightable.
+3
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@@ -0,0 +1,3 @@
$02 + STY $0282
Instruction (storing data in a well-known location) + some part. Trivial, not copyrightable.
+3
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@@ -0,0 +1,3 @@
$02 + STY $0284
Instruction (storing data in a documented location) and a part. Not copyrightable.
+3
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@@ -0,0 +1,3 @@
$02 + STA $D018 + JMP (addres does not match)
One instruction (storing data in a docummented I/O register) + some parts. Not copyrightable.
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@@ -0,0 +1,3 @@
$02 + STX $0281
Instruction (storing data in a documented location) and a part. Not copyrightable.
+3
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@@ -0,0 +1,3 @@
$0B + LDA #$00 + STA (zeropage addreess does not match)
One instruction + some parts. Not copyrightable.
+3
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@@ -0,0 +1,3 @@
$13 + BNE (offset match) + JSR (address does not match)
Instruction + some parts. Not copyrightable.
+1
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@@ -0,0 +1 @@
A byte followed by some 0's - accidental result of ROMs not being full to the last byte. Nothing creative - not copyrightable.
+3
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@@ -0,0 +1,3 @@
PETSCII: (space) MISMATCH
Single word with a space character is not copyrightable. What's more, the MISMATCH word in our BASIC is stored in compressed form - this one must come from Kernal, from out 'panic screen' implementation, something not even present in the original ROM.
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@@ -0,0 +1,3 @@
JSR $FF5B (CINT) + CLI + JMP (vector does not match)
Small part of the initialization routine, basically a sequence of 2 calls. Not creative - not copyrightable.
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@@ -0,0 +1,3 @@
JSR $E5A0 + JMP (address does not match)
Instruction (call to unofficial, but a well-known routine) + some part. Trivial, not copyrightable.
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@@ -0,0 +1,5 @@
AND #$EF + STA $DD00
$DD00 is a hardware register, where one typically set/unset/read individual bits.
Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.
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@@ -0,0 +1,3 @@
PETSCII: IC (space) B
Short text fragment, not even a full syllable. Not copyrightable.
+3
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@@ -0,0 +1,3 @@
JMP $FE25 (MEMTOP) + JMP (address doees not match)
Very small part of Kernal jumptable - part of Kernal API, list of facts without any logic (see also fe25.interop). Not copyrightable.
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@@ -0,0 +1,3 @@
RTS (end of routine) + JSR $E5A0 (setup VIC and I/O)
Similarity only because a routine starts with video chipset initialization - trivial, not copyrightable.
+3
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@@ -0,0 +1,3 @@
$7B + LDA #$FF + STA (zeropage address does not match)
One instruction + some parts. Not copyrightable.
+1
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@@ -0,0 +1 @@
A byte followed by some 0's - accidental result of ROMs not being full to the last byte. Nothing creative - not copyrightable.
+1
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@@ -0,0 +1 @@
A byte followed by some 0's - accidental result of ROMs not being full to the last byte. Nothing creative - not copyrightable.
+3
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@@ -0,0 +1,3 @@
$0281 + STY $0282
Instruction (storing data in a documented location) and a part. Not copyrightable.
+3
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@@ -0,0 +1,3 @@
STA $7A (TXTPTR low byte) + LDA $2C (TXTAB high byte)
$7A and $2C are documented zeropage locations, they are related so it's normal that they are read/written one after another. Here the similarity is limited to just 2 instructions (does not even cover full access of the variables) - this is trivial and thus not copyrightable.
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STA $F4 + RTS (end of subroutine) + JSR (address does not match)
Storing value in a documented memory location, followed by next subroutine started by JSR - not creative, not copyrightable.
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STA $028D + LDY #(value does not match)
Instruction (storing data in a docummented location) + some part. Trivial, not copyrgihtable.
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STA $0290 + LDA (value does not match)
Instruction (storing data in a documented location) and a part. Not copyrightable.
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@@ -0,0 +1,3 @@
STA $0291 + JMP (address does not match)
Instruction (storing data in a well-known location) + some part. Trivial, not copyrightable.
+3
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@@ -0,0 +1,3 @@
STX $DC03 + STX (address does not match)
Instruction (storing data in a documented location) and a part. Not copyrightable.
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@@ -0,0 +1,3 @@
LDA $9A + CMP #$03 + BNE (offset does not match)
Just a check whether the default output device is screen - trivial, not copyrightable.
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@@ -0,0 +1,6 @@
$A6 (part of other compilation unit) + a list of vectors to be copied starting from $0300
Values of the vectors are already present in many autostart software - as it often overrides them,
sometimes changing one to trigger autostart (one of the possible techniques). We have to use the same
vector values to be compatible (in fact, it even complicates our implementation) - see *.interop files
for more details.
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@@ -0,0 +1,3 @@
LDX $D8 + BEQ (skip next instruction) + JMP (address does not match)
Just a check whether insert mode is active - trivial, not copyrightable.
+3
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@@ -0,0 +1,3 @@
LDA #$80 + JSR $FF90 (SETMSG)
There are just two standard parameters of SETMSG - $00 and $80 (to tell Kernal wheether to print out messages or not). This is typical call of Kernal API, not copyrightable.
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@@ -0,0 +1,3 @@
$AB + LDY #$00 + LDA (zeropage addres does not match), Y
Instruction + some parts. Not copyrightable.
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CMP #$03 + BEQ (skip 8 bytes)
Skip few bytes if accumulator value is 3 - not creative, not copyrightable.
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CMP #$0E + BNE (7 bytes forward) + LDA $D018 + ORA #$02 + BNE (offset does not match)
A piece of code that (depending on the PETSCII character) sets/unsets lowercase mode. Not many sane ways exists to do this, some similarities are unevitable. Overall, this code is trivial (and not even fully the same) - not copyrightable.
+3
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@@ -0,0 +1,3 @@
CMP #$12 + BNE (skip 4 bytes) + LDA #(value does not match)
Small part of the PETSCII control codes handling routine - do something if handling character $12 (not even the same thing is done). Not creative - not copyrightable.
+3
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@@ -0,0 +1,3 @@
CMP #$13 + BNE (skip 6 bytes) + JSR (address does not match)
Small part of the PETSCII control codes handling routine - do something if handling character $13. Not creative - not copyrightable.
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@@ -0,0 +1,3 @@
CMP #$8E + BNE (skip 11 bytes) + LDA $D018 + AND#(value does not match)
A piece of code that (depending on the PETSCII character) sets/unsets lowercase mode. Not many sane ways exists to do this, some similarities are unevitable. Overall, this code is trivial (and not even fully the same) - not copyrightable.
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@@ -0,0 +1,3 @@
DEX + STX $DC02
Optimization to store $FF in I/O register, when X is known to be $00 - trivial, not copyrightable.
+3
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@@ -0,0 +1,3 @@
BNE (skip 3 bytes) + JMP ($8000)
Jump through official (documented) vector depending on the flag state, could be 1 instruction in other architectures. Trivial, not copyrightable.
+3
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@@ -0,0 +1,3 @@
BNE (offset match) + LDA #$00 + STA (zeropage address does not match)
If value is 0, clear some zeropage addres (not even the same in original ROMs and our implementation). Nothing creative - not copyrightable.
+3
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@@ -0,0 +1,3 @@
$D1 + STA $F3 + LDA (zeropage address does not match)
Instruction (storing data in a doccumented memory location) + some parts. Not copyrightable.
+3
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@@ -0,0 +1,3 @@
$D8 + BEQ (skip next instruction) + JMP (address does not match)
One instruction + some parts. Not copyrightable.
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@@ -0,0 +1,5 @@
$DD + AND #$EF + STA $DD00 + RTS (end of routine) + LDA $DD00
$DD00 is a hardware register, where one typically set/unset/read individual bits.
Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.
+5
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@@ -0,0 +1,5 @@
$DD + AND #$EF + STA $DD00 + RTS (end of routine) + LDA $DD00 + ORA #$10 + STA $DD00
$DD00 is a hardware register, where one typically set/unset/read individual bits.
Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.
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@@ -0,0 +1,3 @@
$DD + LDA #$3F + STA $DD02
Some part + storing a default value in a documented I/O register - trivial, not copyrightablee.
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@@ -0,0 +1,5 @@
$DF + STA $DD00 + RTS
$DD00 is a hardware register, where one typically set/unset/read individual bits.
Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.
+3
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@@ -0,0 +1,3 @@
$E4 + LDA #$00 + STA (zeropage address does not match)
Instruction + some parts. Not copyrightable.
+3
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@@ -0,0 +1,3 @@
$E9 + LDY #$27 + LDA (zeropage address does not match),Y
Instruction + some parts. Not copyrightable.
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@@ -0,0 +1,3 @@
$EA + LDA $DD00
Instruction and some part - trivial, not copyrightable.
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@@ -0,0 +1,5 @@
$EA + LDA $DD00 + AND #$DF
$DD00 is a hardware register, where one typically set/unset/read individual bits.
Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.
+5
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@@ -0,0 +1,5 @@
$EF + STA $DD00 + RTS (end of a routine) + LDA $DD00 + ORA #$10 + STA $DD00
$DD00 is a hardware register, where one typically set/unset/read individual bits.
Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.
+3
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@@ -0,0 +1,3 @@
$F8 + STA $DC00
Instruction (storing data in a documented location) and a part. Not copyrightable.
+1
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@@ -0,0 +1 @@
A byte followed by some 0's - accidental result of ROMs not being full to the last byte. Nothing creative - not copyrightable.