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Z*) speed optimizations

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FeralChild64 authored and FeralChild64 committed 2021-01-26 00:03:07 +01:00
1 parent 047e7dd56a
commit 2b7de74935
10 files changed
+337 -288
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src/zvm_m65/,aliases_zvm.s
+3 -1
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@@ -26,7 +26,9 @@
!addr REG_R06 = $1B ; refresh counter, bits 0-6 (bit 7 is garbage) !addr REG_R06 = $1B ; refresh counter, bits 0-6 (bit 7 is garbage)
!addr REG_R7 = $1C ; refresh counter, bit 7 (bits 0-6 are 0's) !addr REG_R7 = $1C ; refresh counter, bit 7 (bits 0-6 are 0's)
!addr ADDR_IXY_d = $1D ; 16-bit calculated address IX+d / IY+d XXX - important!!! !addr PTR_IXY_d = $1D ; 16-bit calculated address IX+d / IY+d XXX - important!!!
!addr PTR_DATA = $1D ; data source address XXX is it OK to use the same one?
!addr REG_IFF1 = $1F ; interrupt flip-flop flag 1 !addr REG_IFF1 = $1F ; interrupt flip-flop flag 1
!addr REG_IFF2 = $20 ; interrupt flip-flop flag 2 !addr REG_IFF2 = $20 ; interrupt flip-flop flag 2
src/zvm_m65/z80_instr_bit.s
+178 -178
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File diff suppressed because it is too large. Load diff
src/zvm_m65/z80_instr_exchange.s
+3 -3
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@@ -16,7 +16,7 @@ Z80_instr_EB: ; EX DE,HL
sty REG_E sty REG_E
stx REG_L stx REG_L
rts jmp ZVM_next
Z80_instr_08: ; EX AF,AF'' Z80_instr_08: ; EX AF,AF''
@@ -30,7 +30,7 @@ Z80_instr_08: ; EX AF,AF''
sty REG_F sty REG_F
stx REG_F_SH stx REG_F_SH
rts jmp ZVM_next
Z80_instr_D9: ; EXX Z80_instr_D9: ; EXX
@@ -64,4 +64,4 @@ Z80_instr_D9: ; EXX
sty REG_L sty REG_L
stx REG_L_SH stx REG_L_SH
rts jmp ZVM_next
src/zvm_m65/z80_instr_general.s
+2 -2
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@@ -29,7 +29,7 @@ Z80_instr_ED_5E: ; IM 2
; Real NOP ; Real NOP
Z80_instr_00: ; NOP Z80_instr_00: ; NOP
rts jmp ZVM_next
Z80_instr_F3: ; DI Z80_instr_F3: ; DI
@@ -43,4 +43,4 @@ Z80_instr_FB: ; EI
lda #Z80_PF lda #Z80_PF
sta REG_IFF1 sta REG_IFF1
sta REG_IFF2 sta REG_IFF2
rts jmp ZVM_next
src/zvm_m65/z80_instr_jump.s
+9 -9
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@@ -10,60 +10,60 @@ Z80_instr_C3: ; JP nn
sta REG_PC+0 sta REG_PC+0
jsr (VEC_fetch_value) jsr (VEC_fetch_value)
sta REG_PC+1 sta REG_PC+1
rts jmp ZVM_next
Z80_instr_C2: ; JP NZ,nn Z80_instr_C2: ; JP NZ,nn
bbr6 REG_F,Z80_instr_C3 bbr6 REG_F,Z80_instr_C3
inw REG_PC inw REG_PC
inw REG_PC inw REG_PC
rts jmp ZVM_next
Z80_instr_CA: ; JP Z,nn Z80_instr_CA: ; JP Z,nn
bbs6 REG_F,Z80_instr_C3 bbs6 REG_F,Z80_instr_C3
inw REG_PC inw REG_PC
inw REG_PC inw REG_PC
rts jmp ZVM_next
Z80_instr_D2: ; JP NC,nn Z80_instr_D2: ; JP NC,nn
bbr0 REG_F,Z80_instr_C3 bbr0 REG_F,Z80_instr_C3
inw REG_PC inw REG_PC
inw REG_PC inw REG_PC
rts jmp ZVM_next
Z80_instr_DA: ; JP C,nn Z80_instr_DA: ; JP C,nn
bbs0 REG_F,Z80_instr_C3 bbs0 REG_F,Z80_instr_C3
inw REG_PC inw REG_PC
inw REG_PC inw REG_PC
rts jmp ZVM_next
Z80_instr_E2: ; JP PO,nn Z80_instr_E2: ; JP PO,nn
bbr2 REG_F,Z80_instr_C3 bbr2 REG_F,Z80_instr_C3
inw REG_PC inw REG_PC
inw REG_PC inw REG_PC
rts jmp ZVM_next
Z80_instr_EA: ; JP PE,nn Z80_instr_EA: ; JP PE,nn
bbs2 REG_F,Z80_instr_C3 bbs2 REG_F,Z80_instr_C3
inw REG_PC inw REG_PC
inw REG_PC inw REG_PC
rts jmp ZVM_next
Z80_instr_F2: ; JP P,nn Z80_instr_F2: ; JP P,nn
bbr7 REG_F,Z80_instr_C3 bbr7 REG_F,Z80_instr_C3
inw REG_PC inw REG_PC
inw REG_PC inw REG_PC
rts jmp ZVM_next
Z80_instr_FA: ; JP M,nn Z80_instr_FA: ; JP M,nn
bbs7 REG_F,Z80_instr_C3 bbs7 REG_F,Z80_instr_C3
inw REG_PC inw REG_PC
inw REG_PC inw REG_PC
rts jmp ZVM_next
src/zvm_m65/z80_instr_load_8bit.s
+55 -55
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@@ -12,175 +12,175 @@ Z80_instr_41: ; LD B,C
lda REG_C lda REG_C
sta REG_B sta REG_B
rts jmp ZVM_next
Z80_instr_42: ; LD B,D Z80_instr_42: ; LD B,D
lda REG_D lda REG_D
sta REG_B sta REG_B
rts jmp ZVM_next
Z80_instr_43: ; LD B,E Z80_instr_43: ; LD B,E
lda REG_E lda REG_E
sta REG_B sta REG_B
rts jmp ZVM_next
Z80_instr_44: ; LD B,H Z80_instr_44: ; LD B,H
lda REG_H lda REG_H
sta REG_B sta REG_B
rts jmp ZVM_next
Z80_instr_45: ; LD B,L Z80_instr_45: ; LD B,L
lda REG_L lda REG_L
sta REG_B sta REG_B
rts jmp ZVM_next
Z80_instr_47: ; LD B,A Z80_instr_47: ; LD B,A
lda REG_A lda REG_A
sta REG_B sta REG_B
rts jmp ZVM_next
Z80_instr_48: ; LD C,B Z80_instr_48: ; LD C,B
lda REG_B lda REG_B
sta REG_C sta REG_C
rts jmp ZVM_next
Z80_instr_4A: ; LD C,D Z80_instr_4A: ; LD C,D
lda REG_D lda REG_D
sta REG_C sta REG_C
rts jmp ZVM_next
Z80_instr_4B: ; LD C,E Z80_instr_4B: ; LD C,E
lda REG_E lda REG_E
sta REG_C sta REG_C
rts jmp ZVM_next
Z80_instr_4C: ; LD C,H Z80_instr_4C: ; LD C,H
lda REG_H lda REG_H
sta REG_C sta REG_C
rts jmp ZVM_next
Z80_instr_4D: ; LD C,L Z80_instr_4D: ; LD C,L
lda REG_L lda REG_L
sta REG_C sta REG_C
rts jmp ZVM_next
Z80_instr_4F: ; LD C,A Z80_instr_4F: ; LD C,A
lda REG_A lda REG_A
sta REG_C sta REG_C
rts jmp ZVM_next
Z80_instr_50: ; LD D,B Z80_instr_50: ; LD D,B
lda REG_B lda REG_B
sta REG_D sta REG_D
rts jmp ZVM_next
Z80_instr_51: ; LD D,C Z80_instr_51: ; LD D,C
lda REG_C lda REG_C
sta REG_D sta REG_D
rts jmp ZVM_next
Z80_instr_53: ; LD D,E Z80_instr_53: ; LD D,E
lda REG_E lda REG_E
sta REG_D sta REG_D
rts jmp ZVM_next
Z80_instr_54: ; LD D,H Z80_instr_54: ; LD D,H
lda REG_H lda REG_H
sta REG_D sta REG_D
rts jmp ZVM_next
Z80_instr_55: ; LD D,L Z80_instr_55: ; LD D,L
lda REG_L lda REG_L
sta REG_D sta REG_D
rts jmp ZVM_next
Z80_instr_57: ; LD D,A Z80_instr_57: ; LD D,A
lda REG_A lda REG_A
sta REG_D sta REG_D
rts jmp ZVM_next
Z80_instr_58: ; LD E,B Z80_instr_58: ; LD E,B
lda REG_B lda REG_B
sta REG_E sta REG_E
rts jmp ZVM_next
Z80_instr_59: ; LD E,C Z80_instr_59: ; LD E,C
lda REG_C lda REG_C
sta REG_E sta REG_E
rts jmp ZVM_next
Z80_instr_5A: ; LD E,D Z80_instr_5A: ; LD E,D
lda REG_D lda REG_D
sta REG_E sta REG_E
rts jmp ZVM_next
Z80_instr_5C: ; LD E,H Z80_instr_5C: ; LD E,H
lda REG_H lda REG_H
sta REG_E sta REG_E
rts jmp ZVM_next
Z80_instr_5D: ; LD E,L Z80_instr_5D: ; LD E,L
lda REG_L lda REG_L
sta REG_E sta REG_E
rts jmp ZVM_next
Z80_instr_5F: ; LD E,A Z80_instr_5F: ; LD E,A
lda REG_A lda REG_A
sta REG_E sta REG_E
rts jmp ZVM_next
Z80_instr_60: ; LD H,B Z80_instr_60: ; LD H,B
lda REG_B lda REG_B
sta REG_H sta REG_H
rts jmp ZVM_next
Z80_instr_61: ; LD H,C Z80_instr_61: ; LD H,C
lda REG_C lda REG_C
sta REG_H sta REG_H
rts jmp ZVM_next
Z80_instr_62: ; LD H,D Z80_instr_62: ; LD H,D
lda REG_D lda REG_D
sta REG_H sta REG_H
rts jmp ZVM_next
Z80_instr_63: ; LD H,E Z80_instr_63: ; LD H,E
lda REG_E lda REG_E
sta REG_H sta REG_H
rts jmp ZVM_next
Z80_instr_65: ; LD H,L Z80_instr_65: ; LD H,L
lda REG_L lda REG_L
sta REG_H sta REG_H
rts jmp ZVM_next
Z80_instr_67: ; LD H,A Z80_instr_67: ; LD H,A
@@ -192,73 +192,73 @@ Z80_instr_68: ; LD L,B
lda REG_B lda REG_B
sta REG_L sta REG_L
rts jmp ZVM_next
Z80_instr_69: ; LD L,C Z80_instr_69: ; LD L,C
lda REG_C lda REG_C
sta REG_L sta REG_L
rts jmp ZVM_next
Z80_instr_6A: ; LD L,D Z80_instr_6A: ; LD L,D
lda REG_D lda REG_D
sta REG_L sta REG_L
rts jmp ZVM_next
Z80_instr_6B: ; LD L,E Z80_instr_6B: ; LD L,E
lda REG_E lda REG_E
sta REG_L sta REG_L
rts jmp ZVM_next
Z80_instr_6C: ; LD L,H Z80_instr_6C: ; LD L,H
lda REG_H lda REG_H
sta REG_L sta REG_L
rts jmp ZVM_next
Z80_instr_6F: ; LD L,A Z80_instr_6F: ; LD L,A
lda REG_A lda REG_A
sta REG_L sta REG_L
rts jmp ZVM_next
Z80_instr_78: ; LD A,B Z80_instr_78: ; LD A,B
lda REG_B lda REG_B
sta REG_A sta REG_A
rts jmp ZVM_next
Z80_instr_79: ; LD A,C Z80_instr_79: ; LD A,C
lda REG_C lda REG_C
sta REG_A sta REG_A
rts jmp ZVM_next
Z80_instr_7A: ; LD A,D Z80_instr_7A: ; LD A,D
lda REG_D lda REG_D
sta REG_A sta REG_A
rts jmp ZVM_next
Z80_instr_7B: ; LD A,E Z80_instr_7B: ; LD A,E
lda REG_E lda REG_E
sta REG_A sta REG_A
rts jmp ZVM_next
Z80_instr_7C: ; LD A,H Z80_instr_7C: ; LD A,H
lda REG_H lda REG_H
sta REG_A sta REG_A
rts jmp ZVM_next
Z80_instr_7D: ; LD A,L Z80_instr_7D: ; LD A,L
lda REG_L lda REG_L
sta REG_A sta REG_A
rts jmp ZVM_next
; ;
; load register with immediate value ; load register with immediate value
@@ -268,43 +268,43 @@ Z80_instr_06: ; LD B,n
jsr (VEC_fetch_value) jsr (VEC_fetch_value)
sta REG_B sta REG_B
rts jmp ZVM_next
Z80_instr_0E: ; LD C,n Z80_instr_0E: ; LD C,n
jsr (VEC_fetch_value) jsr (VEC_fetch_value)
sta REG_C sta REG_C
rts jmp ZVM_next
Z80_instr_16: ; LD D,n Z80_instr_16: ; LD D,n
jsr (VEC_fetch_value) jsr (VEC_fetch_value)
sta REG_D sta REG_D
rts jmp ZVM_next
Z80_instr_1E: ; LD E,n Z80_instr_1E: ; LD E,n
jsr (VEC_fetch_value) jsr (VEC_fetch_value)
sta REG_E sta REG_E
rts jmp ZVM_next
Z80_instr_26: ; LD H,n Z80_instr_26: ; LD H,n
jsr (VEC_fetch_value) jsr (VEC_fetch_value)
sta REG_H sta REG_H
rts jmp ZVM_next
Z80_instr_2E: ; LD L,n Z80_instr_2E: ; LD L,n
jsr (VEC_fetch_value) jsr (VEC_fetch_value)
sta REG_L sta REG_L
rts jmp ZVM_next
Z80_instr_3E: ; LD A,n Z80_instr_3E: ; LD A,n
jsr (VEC_fetch_value) jsr (VEC_fetch_value)
sta REG_A sta REG_A
rts jmp ZVM_next
; ;
; load register with memory content (via HL) ; load register with memory content (via HL)
@@ -314,43 +314,43 @@ Z80_instr_46: ; LD B,(HL)
jsr (VEC_fetch_via_HL) jsr (VEC_fetch_via_HL)
sta REG_B sta REG_B
rts jmp ZVM_next
Z80_instr_4E: ; LD C,(HL) Z80_instr_4E: ; LD C,(HL)
jsr (VEC_fetch_via_HL) jsr (VEC_fetch_via_HL)
sta REG_C sta REG_C
rts jmp ZVM_next
Z80_instr_56: ; LD D,(HL) Z80_instr_56: ; LD D,(HL)
jsr (VEC_fetch_via_HL) jsr (VEC_fetch_via_HL)
sta REG_D sta REG_D
rts jmp ZVM_next
Z80_instr_5E: ; LD E,(HL) Z80_instr_5E: ; LD E,(HL)
jsr (VEC_fetch_via_HL) jsr (VEC_fetch_via_HL)
sta REG_E sta REG_E
rts jmp ZVM_next
Z80_instr_66: ; LD H,(HL) Z80_instr_66: ; LD H,(HL)
jsr (VEC_fetch_via_HL) jsr (VEC_fetch_via_HL)
sta REG_H sta REG_H
rts jmp ZVM_next
Z80_instr_6E: ; LD L,(HL) Z80_instr_6E: ; LD L,(HL)
jsr (VEC_fetch_via_HL) jsr (VEC_fetch_via_HL)
sta REG_L sta REG_L
rts jmp ZVM_next
Z80_instr_7E: ; LD A,(HL) Z80_instr_7E: ; LD A,(HL)
jsr (VEC_fetch_via_HL) jsr (VEC_fetch_via_HL)
sta REG_A sta REG_A
rts jmp ZVM_next
; XXX put here LD r,(IX+d) family ; XXX put here LD r,(IX+d) family
; XXX put here LD r,(IY+d) family ; XXX put here LD r,(IY+d) family
src/zvm_m65/z80_instr_math_16bit.s
+12 -12
View File
@@ -7,59 +7,59 @@
Z80_instr_03: ; INC BC Z80_instr_03: ; INC BC
inw REG_C inw REG_C
rts jmp ZVM_next
Z80_instr_13: ; INC DE Z80_instr_13: ; INC DE
inw REG_E inw REG_E
rts jmp ZVM_next
Z80_instr_23: ; INC HL Z80_instr_23: ; INC HL
inw REG_L inw REG_L
rts jmp ZVM_next
Z80_instr_33: ; INC SP Z80_instr_33: ; INC SP
inw REG_SP inw REG_SP
rts jmp ZVM_next
Z80_instr_DD_23: ; INC IX Z80_instr_DD_23: ; INC IX
inw REG_IX inw REG_IX
rts jmp ZVM_next
Z80_instr_FD_23: ; INC IY Z80_instr_FD_23: ; INC IY
inw REG_IY inw REG_IY
rts jmp ZVM_next
Z80_instr_0B: ; DEC BC Z80_instr_0B: ; DEC BC
dew REG_C dew REG_C
rts jmp ZVM_next
Z80_instr_1B: ; DEC DE Z80_instr_1B: ; DEC DE
dew REG_E dew REG_E
rts jmp ZVM_next
Z80_instr_2B: ; DEC HL Z80_instr_2B: ; DEC HL
dew REG_L dew REG_L
rts jmp ZVM_next
Z80_instr_3B: ; DEC SP Z80_instr_3B: ; DEC SP
dew REG_SP dew REG_SP
rts jmp ZVM_next
Z80_instr_DD_2B: ; DEC IX Z80_instr_DD_2B: ; DEC IX
dew REG_IX dew REG_IX
rts jmp ZVM_next
Z80_instr_FD_2B: ; DEC IY Z80_instr_FD_2B: ; DEC IY
dew REG_IY dew REG_IY
rts jmp ZVM_next
src/zvm_m65/z80_instr_math_8bit.s
+8 -8
View File
@@ -60,14 +60,14 @@ Z80_common_INC:
and #(0xFF - Z80_SF - Z80_ZF - Z80_HF - Z80_VF - Z80_NF) and #(0xFF - Z80_SF - Z80_ZF - Z80_HF - Z80_VF - Z80_NF)
ora z80_ftable_INC, x ora z80_ftable_INC, x
sta REG_F sta REG_F
rts jmp ZVM_next
Z80_instr_34: ; INC (HL) Z80_instr_34: ; INC (HL)
jsr (VEC_fetch_via_HL) jsr (VEC_fetch_via_HL)
tax tax
inc inc
jsr ZVM_store_back sta [PTR_DATA],z
bra Z80_common_INC bra Z80_common_INC
Z80_instr_DD_34: ; INC (IX+d) Z80_instr_DD_34: ; INC (IX+d)
@@ -75,7 +75,7 @@ Z80_instr_DD_34: ; INC (IX+d)
jsr (VEC_fetch_via_IX_d) jsr (VEC_fetch_via_IX_d)
tax tax
inc inc
jsr ZVM_store_back sta [PTR_DATA],z
bra Z80_common_INC bra Z80_common_INC
Z80_instr_FD_34: ; INC (IY+d) Z80_instr_FD_34: ; INC (IY+d)
@@ -83,7 +83,7 @@ Z80_instr_FD_34: ; INC (IY+d)
jsr (VEC_fetch_via_IY_d) jsr (VEC_fetch_via_IY_d)
tax tax
inc inc
jsr ZVM_store_back sta [PTR_DATA],z
bra Z80_common_INC bra Z80_common_INC
Z80_instr_05: ; DEC B Z80_instr_05: ; DEC B
@@ -135,14 +135,14 @@ Z80_common_DEC:
and #(0xFF - Z80_SF - Z80_ZF - Z80_HF - Z80_VF - Z80_NF) and #(0xFF - Z80_SF - Z80_ZF - Z80_HF - Z80_VF - Z80_NF)
ora z80_ftable_DEC, x ora z80_ftable_DEC, x
sta REG_F sta REG_F
rts jmp ZVM_next
Z80_instr_35: ; DEC (HL) Z80_instr_35: ; DEC (HL)
jsr (VEC_fetch_via_HL) jsr (VEC_fetch_via_HL)
tax tax
dec dec
jsr ZVM_store_back sta [PTR_DATA],z
bra Z80_common_DEC bra Z80_common_DEC
Z80_instr_DD_35: ; DEC (IX+d) Z80_instr_DD_35: ; DEC (IX+d)
@@ -150,7 +150,7 @@ Z80_instr_DD_35: ; DEC (IX+d)
jsr (VEC_fetch_via_IX_d) jsr (VEC_fetch_via_IX_d)
tax tax
dec dec
jsr ZVM_store_back sta [PTR_DATA],z
bra Z80_common_DEC bra Z80_common_DEC
Z80_instr_FD_35: ; DEC (IY+d) Z80_instr_FD_35: ; DEC (IY+d)
@@ -158,5 +158,5 @@ Z80_instr_FD_35: ; DEC (IY+d)
jsr (VEC_fetch_via_IY_d) jsr (VEC_fetch_via_IY_d)
tax tax
dec dec
jsr ZVM_store_back sta [PTR_DATA],z
bra Z80_common_DEC bra Z80_common_DEC
src/zvm_m65/zvm_banking.s
+54 -12
View File
@@ -146,24 +146,66 @@ ZVM_fetch_value_bank_0:
ZVM_fetch_value_bank_1: ZVM_fetch_value_bank_1:
ZVM_fetch_stack_bank_0: ZVM_fetch_stack_bank_0:
ZVM_fetch_stack_bank_1: ZVM_fetch_stack_bank_1:
ZVM_store_stack_bank_0:
ZVM_store_stack_bank_1:
ZVM_fetch_via_HL_bank_0: ZVM_fetch_via_HL_bank_0:
ZVM_fetch_via_HL_bank_1: ZVM_fetch_via_HL_bank_1:
ZVM_store_via_HL_bank_0:
ZVM_store_via_HL_bank_1:
ZVM_fetch_via_IX_d_bank_0: ZVM_fetch_via_IX_d_bank_0:
ZVM_fetch_via_IX_d_bank_1: ZVM_fetch_via_IX_d_bank_1:
ZVM_fetch_via_IY_d_bank_0: ZVM_fetch_via_IY_d_bank_0:
ZVM_fetch_via_IY_d_bank_1: ZVM_fetch_via_IY_d_bank_1:
ZVM_store_via_IX_d_bank_0:
ZVM_store_via_IX_d_bank_1:
ZVM_store_via_IY_d_bank_0:
ZVM_store_via_IY_d_bank_1:
ZVM_fetch_via_nn_bank_0: ZVM_fetch_via_nn_bank_0:
ZVM_fetch_via_nn_bank_1: ZVM_fetch_via_nn_bank_1:
ZVM_store_via_nn_bank_0:
ZVM_store_via_nn_bank_1:
ZVM_store_back:
; XXX implement these ; XXX
rts
ZVM_store_stack_bank_0:
; XXX
jmp ZVM_next
ZVM_store_stack_bank_1:
; XXX
jmp ZVM_next
ZVM_store_via_HL_bank_0:
; XXX
jmp ZVM_next
ZVM_store_via_HL_bank_1:
; XXX
jmp ZVM_next
ZVM_store_via_IX_d_bank_0:
; XXX
jmp ZVM_next
ZVM_store_via_IX_d_bank_1:
; XXX
jmp ZVM_next
ZVM_store_via_IY_d_bank_0:
; XXX
jmp ZVM_next
ZVM_store_via_IY_d_bank_1:
; XXX
jmp ZVM_next
ZVM_store_via_nn_bank_0:
; XXX
jmp ZVM_next
ZVM_store_via_nn_bank_1:
; XXX
jmp ZVM_next
src/zvm_m65/zvm_core.s
+13 -8
View File
@@ -7,10 +7,14 @@ ZVM_entry:
jsr ZVM_init jsr ZVM_init
; XXX fetch BDOS and Command Processor ; XXX fetch BDOS and Command Processor
jmp ZVM_run jmp ZVM_next
ZVM_init: ZVM_init:
; .Z is required to be 0 all the time
ldz #$00
; Reset all the registers ; Reset all the registers
lda #$00 lda #$00
@@ -24,9 +28,14 @@ ZVM_init:
; XXX what is the initial SP value? ; XXX what is the initial SP value?
; XXX clean memory ; XXX clean memory
jmp ZVM_set_bank_0 jmp ZVM_set_bank_1
ZVM_run:
ZVM_store_next:
sta [PTR_DATA],z
ZVM_next: ; fetch and execute next opcode
; CPU main loop ; CPU main loop
@@ -85,10 +94,6 @@ ZVM_run: