handle all 4 SIDs on Mega65, tape turbo SFX should play on both left and right channels

This commit is contained in:
FeralChild64 committed 2020-05-26 22:21:23 +02:00
1 parent 82b7e85b48
commit 31b3bc38c9
8 files changed
+61 -5

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+15 -2
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@@ -59,10 +59,12 @@ IOINIT:
// Now silence the SID chip(s), depending on the configuration - we want them silent ASAP
//
// First the standard chip (skip if it is covered by whole $D4XX range)
lda #$00
#if !CONFIG_MB_MEGA65
// First the standard chip (skip if it is covered by whole $D4XX range)
#if !CONFIG_SID_D4XX
sta SID_SIGVOL
#endif // !CONFIG_SID_D4XX
@@ -100,6 +102,17 @@ IOINIT:
#endif // CONFIG_SID_D4XX || CONFIG_SID_D5XX
#else
// Mega65 specific handling - it contains 4 SIDs
sta SID_SIGVOL + __SID_R1_OFFSET
sta SID_SIGVOL + __SID_R2_OFFSET
sta SID_SIGVOL + __SID_L1_OFFSET
sta SID_SIGVOL + __SID_L2_OFFSET
#endif // CONFIG_MB_MEGA65
//
// Now continue the CIAs initialization
//
+5
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@@ -17,7 +17,12 @@ tape_common_autodetect:
lda #$0B
sta VIC_EXTCOL
lda #$00
#if CONFIG_MB_MEGA65
sta SID_SIGVOL + __SID_R1_OFFSET
sta SID_SIGVOL + __SID_L1_OFFSET
#else
sta SID_SIGVOL
#endif
// FALLTROUGH
+15
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@@ -15,7 +15,22 @@ tape_clean_sid:
lda #$00
ldy #$1C
!:
#if CONFIG_MB_MEGA65
// It should be safer than cleaning whole $D400-D47C range
sta __SID_BASE + __SID_R1_OFFSET, y
sta __SID_BASE + __SID_R2_OFFSET, y
sta __SID_BASE + __SID_L1_OFFSET, y
sta __SID_BASE + __SID_L2_OFFSET, y
#else
sta __SID_BASE, y
#endif
dey
bpl !-
+10
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@@ -23,7 +23,12 @@ tape_turbo_get_bit:
sta __turbo_half_S // store half of the last measurement result for short pulse
lda #$01
#if CONFIG_MB_MEGA65
sta SID_SIGVOL + __SID_R1_OFFSET
sta SID_SIGVOL + __SID_L1_OFFSET
#else
sta SID_SIGVOL
#endif
lda #$06
sta VIC_EXTCOL
sec
@@ -34,7 +39,12 @@ tape_turbo_get_bit:
sta __turbo_half_L // store half of the last measurement result for long pulse
lda #$00
#if CONFIG_MB_MEGA65
sta SID_SIGVOL + __SID_R1_OFFSET
sta SID_SIGVOL + __SID_L1_OFFSET
#else
sta SID_SIGVOL
#endif
sta VIC_EXTCOL
clc
rts