started JiffyDOS byte fetch synchronization

This commit is contained in:
FeralChild64 committed 2019-11-28 20:12:09 +01:00
1 parent e29bf33a83
commit 34d12e26ac
3 files changed
+18 -14

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+2 -2
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@@ -308,7 +308,7 @@
#elif CONFIG_TAPE_TURBO
.eval features_str = ADD_FEATURE(features_str, "TAPE LOAD TURBO")
#elif CONFIG_TAPE_NORMAL && CONFIG_TAPE_TURBO
.eval features_str = ADD_FEATURE(features_str, "TAPE LOAD NORMAL+TURBO")
.eval features_str = ADD_FEATURE(features_str, "TAPE LOAD NORMAL TURBO")
#endif
.eval feature_new_line = true
@@ -317,7 +317,7 @@
#if !CONFIG_IEC_JIFFYDOS
.eval features_str = ADD_FEATURE(features_str, "IEC")
#else
.eval features_str = ADD_FEATURE(features_str, "IEC+JIFFY DEV")
.eval features_str = ADD_FEATURE(features_str, "IEC JIFFY-DEV")
#endif
#endif
+16 -2
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@@ -122,29 +122,43 @@ iec_rx_byte_jiffydos:
// Ask device to start sending bits
stx CIA2_PRA // cycles: 4
// Retrieve byte XXX count cycles, synchronize
// XXX we have to wait 20 cycles??? seriously??? what the hell shall we do here???
pla // 4 cycles
pha // 3 cycles
pla // 4 cycles
pha // 3 cycles
nop // 2 cycles
nop // 2 cycles
nop // 2 cycles
// Get bits, cycles: 4 + 2 + 2 = 8
lda CIA2_PRA // bits 0 and 1 on CLK/DATA
lsr
lsr
// Wait for the drive, cycles: 2
nop
// Get bits, cycles: 4 + 2 + 2 = 8
ora CIA2_PRA // bits 2 and 3 on CLK/DATA
lsr
lsr
// Get bits, cycles: 3 + 4 + 2 + 2 = 11
eor C3PO
eor CIA2_PRA // bits 4 and 5 on CLK/DATA
lsr
lsr
// Get bits, cycles: 3 + 4 = 7
eor C3PO
eor CIA2_PRA // bits 6 and 7 on CLK/DATA
tax
// XXX CLK and DATA active = EOI
lda CIA2_PRA
// FALLTROUGH
jiffydos_return_success:
-10
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@@ -26,16 +26,6 @@ TALK:
// Encode and execute the command
ora #$40
#if CONFIG_IEC_JIFFYDOS
// XXX temporary, until receiving is implemented too
sta TBTCNT
lda #$00 // standard protocol
sta IECPROTO
jmp iec_tx_command
#endif // CONFIG_IEC_JIFFYDOS
common_talk_listen: // common part of TALK and LISTEN
sta TBTCNT