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implemented 32 more Z80 instructions

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This commit is contained in:
FeralChild64 committed 2020-12-17 20:54:59 +01:00
1 parent de9d935c70
commit 376cf2506d
2 files changed
+242 -37
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src/zvm_m65/z80_math_8bit.s
+190 -4
View File
@@ -445,8 +445,101 @@ Z80_instr_CB_FE: ; SET 7,(HL)
ora #%10000000
jmp ZVM_store_back
; XXX put SET b,(IX+d) instructions here
; XXX put SET b,(IY+d) instructions here
Z80_instr_DDCB_C6: ; SET 0,(IX+d)
jsr (VEC_fetch_via_IX_d)
ora #%00000001
jmp ZVM_store_back
Z80_instr_DDCB_CE: ; SET 1,(IX+d)
jsr (VEC_fetch_via_IX_d)
ora #%00000010
jmp ZVM_store_back
Z80_instr_DDCB_D6: ; SET 2,(IX+d)
jsr (VEC_fetch_via_IX_d)
ora #%00000100
jmp ZVM_store_back
Z80_instr_DDCB_DE: ; SET 3,(IX+d)
jsr (VEC_fetch_via_IX_d)
ora #%00001000
jmp ZVM_store_back
Z80_instr_DDCB_E6: ; SET 4,(IX+d)
jsr (VEC_fetch_via_IX_d)
ora #%00010000
jmp ZVM_store_back
Z80_instr_DDCB_EE: ; SET 5,(IX+d)
jsr (VEC_fetch_via_IX_d)
ora #%00100000
jmp ZVM_store_back
Z80_instr_DDCB_F6: ; SET 6,(IX+d)
jsr (VEC_fetch_via_IX_d)
ora #%01000000
jmp ZVM_store_back
Z80_instr_DDCB_FE: ; SET 7,(IX+d)
jsr (VEC_fetch_via_IX_d)
ora #%10000000
jmp ZVM_store_back
Z80_instr_FDCB_C6: ; SET 0,(IY+d)
jsr (VEC_fetch_via_IY_d)
ora #%00000001
jmp ZVM_store_back
Z80_instr_FDCB_CE: ; SET 1,(IY+d)
jsr (VEC_fetch_via_IY_d)
ora #%00000010
jmp ZVM_store_back
Z80_instr_FDCB_D6: ; SET 2,(IY+d)
jsr (VEC_fetch_via_IY_d)
ora #%00000100
jmp ZVM_store_back
Z80_instr_FDCB_DE: ; SET 3,(IY+d)
jsr (VEC_fetch_via_IY_d)
ora #%00001000
jmp ZVM_store_back
Z80_instr_FDCB_E6: ; SET 4,(IY+d)
jsr (VEC_fetch_via_IY_d)
ora #%00010000
jmp ZVM_store_back
Z80_instr_FDCB_EE: ; SET 5,(IY+d)
jsr (VEC_fetch_via_IY_d)
ora #%00100000
jmp ZVM_store_back
Z80_instr_FDCB_F6: ; SET 6,(IY+d)
jsr (VEC_fetch_via_IY_d)
ora #%01000000
jmp ZVM_store_back
Z80_instr_FDCB_FE: ; SET 7,(IY+d)
jsr (VEC_fetch_via_IY_d)
ora #%10000000
jmp ZVM_store_back
Z80_instr_CB_80: ; RES 0,B
@@ -888,5 +981,98 @@ Z80_instr_CB_BE: ; RES 7,(HL)
and #%01111111
jmp ZVM_store_back
; XXX put RES b,(IX+d) instructions here
; XXX put RES b,(IY+d) instructions here
Z80_instr_DDCB_86: ; RES 0,(IX+d)
jsr (VEC_fetch_via_IX_d)
and #%11111110
jmp ZVM_store_back
Z80_instr_DDCB_8E: ; RES 1,(IX+d)
jsr (VEC_fetch_via_IX_d)
and #%11111101
jmp ZVM_store_back
Z80_instr_DDCB_96: ; RES 2,(IX+d)
jsr (VEC_fetch_via_IX_d)
and #%11111011
jmp ZVM_store_back
Z80_instr_DDCB_9E: ; RES 3,(IX+d)
jsr (VEC_fetch_via_IX_d)
and #%11110111
jmp ZVM_store_back
Z80_instr_DDCB_A6: ; RES 4,(IX+d)
jsr (VEC_fetch_via_IX_d)
and #%11101111
jmp ZVM_store_back
Z80_instr_DDCB_AE: ; RES 5,(IX+d)
jsr (VEC_fetch_via_IX_d)
and #%11011111
jmp ZVM_store_back
Z80_instr_DDCB_B6: ; RES 6,(IX+d)
jsr (VEC_fetch_via_IX_d)
and #%10111111
jmp ZVM_store_back
Z80_instr_DDCB_BE: ; RES 7,(IX+d)
jsr (VEC_fetch_via_IX_d)
and #%01111111
jmp ZVM_store_back
Z80_instr_FDCB_86: ; RES 0,(IY+d)
jsr (VEC_fetch_via_IY_d)
and #%11111110
jmp ZVM_store_back
Z80_instr_FDCB_8E: ; RES 1,(IY+d)
jsr (VEC_fetch_via_IY_d)
and #%11111101
jmp ZVM_store_back
Z80_instr_FDCB_96: ; RES 2,(IY+d)
jsr (VEC_fetch_via_IY_d)
and #%11111011
jmp ZVM_store_back
Z80_instr_FDCB_9E: ; RES 3,(IY+d)
jsr (VEC_fetch_via_IY_d)
and #%11110111
jmp ZVM_store_back
Z80_instr_FDCB_A6: ; RES 4,(IY+d)
jsr (VEC_fetch_via_IY_d)
and #%11101111
jmp ZVM_store_back
Z80_instr_FDCB_AE: ; RES 5,(IY+d)
jsr (VEC_fetch_via_IY_d)
and #%11011111
jmp ZVM_store_back
Z80_instr_FDCB_B6: ; RES 6,(IY+d)
jsr (VEC_fetch_via_IY_d)
and #%10111111
jmp ZVM_store_back
Z80_instr_FDCB_BE: ; RES 7,(IY+d)
jsr (VEC_fetch_via_IY_d)
and #%01111111
jmp ZVM_store_back
src/zvm_m65/zvm_core.s
+52 -33
View File
@@ -44,6 +44,56 @@ ZVM_run:
;
; Not implemented yet - XXX implement them!
;
@@ -181,7 +231,7 @@ Z80_instr_CA: ; JP Z,nn
Z80_instr_CB: ; #CB
Z80_instr_CC: ; CALL Z,nn
Z80_instr_CD: ; CALL nn
Z80_instr_CE: ; ADC A,n
Z80_instr_CE: ; ADC A,n
Z80_instr_CF: ; RST 08H
Z80_instr_D0: ; RET NC
Z80_instr_D1: ; POP DE
@@ -498,22 +548,6 @@ Z80_instr_DDCB_66: ; BIT 4,(IX+d)
Z80_instr_DDCB_6E: ; BIT 5,(IX+d)
Z80_instr_DDCB_76: ; BIT 6,(IX+d)
Z80_instr_DDCB_7E: ; BIT 7,(IX+d)
Z80_instr_DDCB_86: ; RES 0,(IX+d)
Z80_instr_DDCB_8E: ; RES 1,(IX+d)
Z80_instr_DDCB_96: ; RES 2,(IX+d)
Z80_instr_DDCB_9E: ; RES 3,(IX+d)
Z80_instr_DDCB_A6: ; RES 4,(IX+d)
Z80_instr_DDCB_AE: ; RES 5,(IX+d)
Z80_instr_DDCB_B6: ; RES 6,(IX+d)
Z80_instr_DDCB_BE: ; RES 7,(IX+d)
Z80_instr_DDCB_C6: ; SET 0,(IX+d)
Z80_instr_DDCB_CE: ; SET 1,(IX+d)
Z80_instr_DDCB_D6: ; SET 2,(IX+d)
Z80_instr_DDCB_DE: ; SET 3,(IX+d)
Z80_instr_DDCB_E6: ; SET 4,(IX+d)
Z80_instr_DDCB_EE: ; SET 5,(IX+d)
Z80_instr_DDCB_F6: ; SET 6,(IX+d)
Z80_instr_DDCB_FE: ; SET 7,(IX+d)
Z80_instr_FDCB_06: ; RLC (IY+d)
Z80_instr_FDCB_0E: ; RRC (IY+d)
Z80_instr_FDCB_16: ; RL (IY+d)
@@ -529,22 +563,7 @@ Z80_instr_FDCB_66: ; BIT 4,(IY+d)
Z80_instr_FDCB_6E: ; BIT 5,(IY+d)
Z80_instr_FDCB_76: ; BIT 6,(IY+d)
Z80_instr_FDCB_7E: ; BIT 7,(IY+d)
Z80_instr_FDCB_86: ; RES 0,(IY+d)
Z80_instr_FDCB_8E: ; RES 1,(IY+d)
Z80_instr_FDCB_96: ; RES 2,(IY+d)
Z80_instr_FDCB_9E: ; RES 3,(IY+d)
Z80_instr_FDCB_A6: ; RES 4,(IY+d)
Z80_instr_FDCB_AE: ; RES 5,(IY+d)
Z80_instr_FDCB_B6: ; RES 6,(IY+d)
Z80_instr_FDCB_BE: ; RES 7,(IY+d)
Z80_instr_FDCB_C6: ; SET 0,(IY+d)
Z80_instr_FDCB_CE: ; SET 1,(IY+d)
Z80_instr_FDCB_D6: ; SET 2,(IY+d)
Z80_instr_FDCB_DE: ; SET 3,(IY+d)
Z80_instr_FDCB_E6: ; SET 4,(IY+d)
Z80_instr_FDCB_EE: ; SET 5,(IY+d)
Z80_instr_FDCB_F6: ; SET 6,(IY+d)
Z80_instr_FDCB_FE: ; SET 7,(IY+d)
rts ; XXX
; XXX add 'illegal' instructions