separate directory for fast IEC routines
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@@ -19,6 +19,7 @@ SRCDIR_KERNAL = $(SRCDIR_COMMON) \
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c64/kernal/,stubs \
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c64/kernal/assets \
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c64/kernal/iec \
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c64/kernal/iec_fast \
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c64/kernal/init \
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c64/kernal/interrupts \
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c64/kernal/iostack \
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@@ -1,238 +0,0 @@
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//
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// JiffyDOS protocol support for IEC
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//
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// XXX make it work
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// XXX split into multiple files
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#if CONFIG_IEC_JIFFYDOS
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// JiffyDOS timing regime is very strict - before transmitting anything
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// we need to disable sprites and (if screen is not disabled) wait for
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// appropriate moment, so that no badline interruption can happen
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iec_tx_byte_jiffydos:
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// Timing is critical, do not allow interrupts
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sei
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// If EOI requested (carry flag set), mark this in IECPROTO as 0
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bcc !+
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dec IECPROTO // turns 1 into 0
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!:
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// Store .X and .Y on the stack - preserve them
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phx_trash_a
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phy_trash_a
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// Store previous sprite status on stack
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jsr jiffydos_prepare_for_transfer
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pha
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// Prepare nibbles to send
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lda TBTCNT
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and #$0F
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tax
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lda iec_jiffydos_bittable, X // low nibble has to be encoded
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pha
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lda TBTCNT
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and #$F0
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pha
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// Prepare value for device notification
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ldx C3PO
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// Wait till receiver is ready
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jsr iec_wait_for_data_release
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// Wait till it is safe to send data
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jsr jiffydos_wait_line
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// Notify device that we are going to send byte by releasing everything
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stx CIA2_PRA // cycles: 4
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// Send high nibble; cycles: 4 + 3 + 4 + 2 + 2 + 2 + 3 + 4 = 24
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pla // retrieve high nibble from stack
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ora C3PO // restore VIC-II and RS-232 bits
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sta CIA2_PRA // bits 4 and 5 on CLK/DATA
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lsr // move bits 6 and 7 to positions 4 and 5
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lsr
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and #%00110000 // clear everything but CLK/DATA
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ora C3PO
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sta CIA2_PRA // bits 6 and 7 on CLK/DATA
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// Send low nibble; cycles: 4 + 3 + 4 + 2 + 2 + 2 + 4 = 21
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pla // retrieve low nibble from stack
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ora C3PO // restore VIC-II and RS-232 bits
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sta CIA2_PRA
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lsr
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lsr
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and #%00110000 // clear everything but CLK/DATA
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sta CIA2_PRA
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// Signal EOI if needed; cycles till no EOI: 3 + 3 + 2 + 2 + 4 = 14
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lda C3PO
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ldx IECPROTO
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beq iec_tx_byte_jiffydos_wait_eoi
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// FALLTROUGH
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iec_tx_byte_jiffydos_finalize:
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ora #BIT_CIA2_PRA_CLK_OUT // pull CLK
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sta CIA2_PRA
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// Restore proper IECPROTO value
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lda #$01
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sta IECPROTO
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// Re-enable sprites and interrupts
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pla
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sta VIC_SPENA
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cli
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// Return success
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jmp iec_return_success
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iec_tx_byte_jiffydos_wait_eoi:
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jsr iec_wait20us // XXX is it enough?
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lda C3PO
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jmp iec_tx_byte_jiffydos_finalize
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iec_rx_byte_jiffydos:
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// Timing is critical, do not allow interrupts
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sei
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// Store .X and .Y on the stack - preserve them
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phx_trash_a
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phy_trash_a
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// Store previous sprite status on stack
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jsr jiffydos_prepare_for_transfer
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pha
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// Wait until device is ready to send
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jsr iec_wait_for_clk_release
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// Prepare 'start sending' message
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lda CIA2_PRA
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and #$FF - BIT_CIA2_PRA_DAT_OUT // release
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tax
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// Wait for appropriate moment
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jsr jiffydos_wait_line
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// Ask device to start sending bits
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stx CIA2_PRA // cycles: 4
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// XXX we have to wait 20 cycles??? seriously??? what the hell shall we do here???
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pla // 4 cycles
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pha // 3 cycles
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pla // 4 cycles
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pha // 3 cycles
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nop // 2 cycles
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nop // 2 cycles
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nop // 2 cycles
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// Get bits, cycles: 4 + 2 + 2 = 8
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lda CIA2_PRA // bits 0 and 1 on CLK/DATA
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lsr
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lsr
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// Wait for the drive, cycles: 2
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nop
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// Get bits, cycles: 4 + 2 + 2 = 8
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ora CIA2_PRA // bits 2 and 3 on CLK/DATA
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lsr
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lsr
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// Get bits, cycles: 3 + 4 + 2 + 2 = 11
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eor C3PO
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eor CIA2_PRA // bits 4 and 5 on CLK/DATA
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lsr
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lsr
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// Get bits, cycles: 3 + 4 = 7
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eor C3PO
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eor CIA2_PRA // bits 6 and 7 on CLK/DATA
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// Preserve read byte
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sta TBTCNT // $A4 is a byte buffer according to http://sta.c64.org/cbm64mem.html
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// Retrieve status bits
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lda CIA2_PRA
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tax
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// Pull DATA at the end
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ora #BIT_CIA2_PRA_DAT_OUT
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sta CIA2_PRA
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// Check for EOI
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txa
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bmi !+
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jsr kernalstatus_EOI
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!:
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// Restore proper IECPROTO value
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lda #$01
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sta IECPROTO
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// Re-enable sprites
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pla
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sta VIC_SPENA
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// End byte reception
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jmp iec_rx_end
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jiffydos_wait_line:
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lda VIC_SCROLY
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and #$10
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beq jiffydos_wait_line_done // screen is disabled, no need to watch for badlines
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// Avoid 2 lines before the badline, otherwise VIC will ruin the synchronization
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lda VIC_RASTER
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cmp #$2E
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bcc jiffydos_wait_line_done // we are safe, border - lot of time till badline
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!:
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lda VIC_RASTER // carry+ is definitely set here!
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sbc VIC_SCROLY
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and #$07 // we want 8 lowest bits
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cmp #$06
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bcs !-
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jiffydos_wait_line_done:
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rts
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jiffydos_prepare_for_transfer:
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// We need to preserve 3 lowest bits of CIA2_PRA, they contain important
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// data - fortunately, the bits are never changed by external devices
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// Use C3PO for this, as afterwards we have to set there 0 nevertheless
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lda CIA2_PRA
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and #%00000111
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sta C3PO
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// Hide sprites
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lda VIC_SPENA
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ldx #$00
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stx VIC_SPENA
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rts
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#endif // CONFIG_IEC_JIFFYDOS
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@@ -0,0 +1,97 @@
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//
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// JiffyDOS protocol support for IEC - byte reception
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//
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#if CONFIG_IEC_JIFFYDOS
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iec_rx_byte_jiffydos:
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// Timing is critical, do not allow interrupts
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sei
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// Store .X and .Y on the stack - preserve them
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phx_trash_a
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phy_trash_a
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// Store previous sprite status on stack
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jsr jiffydos_prepare
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pha
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// Wait until device is ready to send
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jsr iec_wait_for_clk_release
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// Prepare 'start sending' message
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lda CIA2_PRA
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and #$FF - BIT_CIA2_PRA_DAT_OUT // release
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tax
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// Wait for appropriate moment
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jsr jiffydos_wait_line
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// Ask device to start sending bits
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stx CIA2_PRA // cycles: 4
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// XXX we have to wait 20 cycles??? seriously??? what the hell shall we do here???
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pla // 4 cycles
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pha // 3 cycles
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pla // 4 cycles
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pha // 3 cycles
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nop // 2 cycles
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nop // 2 cycles
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nop // 2 cycles
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// Get bits, cycles: 4 + 2 + 2 = 8
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lda CIA2_PRA // bits 0 and 1 on CLK/DATA
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lsr
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lsr
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// Wait for the drive, cycles: 2
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nop
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// Get bits, cycles: 4 + 2 + 2 = 8
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ora CIA2_PRA // bits 2 and 3 on CLK/DATA
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lsr
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lsr
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// Get bits, cycles: 3 + 4 + 2 + 2 = 11
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eor C3PO
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eor CIA2_PRA // bits 4 and 5 on CLK/DATA
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lsr
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lsr
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// Get bits, cycles: 3 + 4 = 7
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eor C3PO
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eor CIA2_PRA // bits 6 and 7 on CLK/DATA
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// Preserve read byte
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sta TBTCNT // $A4 is a byte buffer according to http://sta.c64.org/cbm64mem.html
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// Retrieve status bits
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lda CIA2_PRA
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tax
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// Pull DATA at the end
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ora #BIT_CIA2_PRA_DAT_OUT
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sta CIA2_PRA
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// Check for EOI
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txa
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bmi !+
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jsr kernalstatus_EOI
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!:
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// Restore proper IECPROTO value
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lda #$01
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sta IECPROTO
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// Re-enable sprites
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pla
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sta VIC_SPENA
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// End byte reception
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jmp iec_rx_end
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#endif // CONFIG_IEC_JIFFYDOS
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File renamed without changes.
@@ -0,0 +1,102 @@
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//
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// JiffyDOS protocol support for IEC - byte transfer
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//
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// XXX make it work
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#if CONFIG_IEC_JIFFYDOS
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iec_tx_byte_jiffydos:
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// Timing is critical, do not allow interrupts
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sei
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// If EOI requested (carry flag set), mark this in IECPROTO as 0
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bcc !+
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dec IECPROTO // turns 1 into 0
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!:
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// Store .X and .Y on the stack - preserve them
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phx_trash_a
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phy_trash_a
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// Store previous sprite status on stack
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jsr jiffydos_prepare
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pha
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// Prepare nibbles to send
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lda TBTCNT
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and #$0F
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tax
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lda jiffydos_bittable, X // low nibble has to be encoded
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pha
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lda TBTCNT
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and #$F0
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pha
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// Prepare value for device notification
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ldx C3PO
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// Wait till receiver is ready
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jsr iec_wait_for_data_release
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// Wait till it is safe to send data
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jsr jiffydos_wait_line
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// Notify device that we are going to send byte by releasing everything
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stx CIA2_PRA // cycles: 4
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// Send high nibble; cycles: 4 + 3 + 4 + 2 + 2 + 2 + 3 + 4 = 24
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pla // retrieve high nibble from stack
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ora C3PO // restore VIC-II and RS-232 bits
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sta CIA2_PRA // bits 4 and 5 on CLK/DATA
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lsr // move bits 6 and 7 to positions 4 and 5
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lsr
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and #%00110000 // clear everything but CLK/DATA
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ora C3PO
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sta CIA2_PRA // bits 6 and 7 on CLK/DATA
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// Send low nibble; cycles: 4 + 3 + 4 + 2 + 2 + 2 + 4 = 21
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pla // retrieve low nibble from stack
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ora C3PO // restore VIC-II and RS-232 bits
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sta CIA2_PRA
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lsr
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lsr
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and #%00110000 // clear everything but CLK/DATA
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sta CIA2_PRA
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// Signal EOI if needed; cycles till no EOI: 3 + 3 + 2 + 2 + 4 = 14
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lda C3PO
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ldx IECPROTO
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beq iec_tx_byte_jiffydos_wait_eoi
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// FALLTROUGH
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iec_tx_byte_jiffydos_finalize:
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ora #BIT_CIA2_PRA_CLK_OUT // pull CLK
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sta CIA2_PRA
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// Restore proper IECPROTO value
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lda #$01
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sta IECPROTO
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// Re-enable sprites and interrupts
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pla
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sta VIC_SPENA
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cli
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// Return success
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jmp iec_return_success
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iec_tx_byte_jiffydos_wait_eoi:
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jsr iec_wait20us // XXX is it enough?
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lda C3PO
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jmp iec_tx_byte_jiffydos_finalize
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#endif // CONFIG_IEC_JIFFYDOS
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File renamed without changes.
@@ -15,7 +15,7 @@
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#if CONFIG_IEC_JIFFYDOS
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iec_jiffydos_bittable:
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jiffydos_bittable:
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.byte $00
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.byte $80 // $10 + $70
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@@ -0,0 +1,29 @@
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//
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// JiffyDOS transfer preparation routine
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//
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#if CONFIG_IEC_JIFFYDOS
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jiffydos_prepare:
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// We need to preserve 3 lowest bits of CIA2_PRA, they contain important
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// data - fortunately, the bits are never changed by external devices
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// Use C3PO for this, as afterwards we have to set there 0 nevertheless
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lda CIA2_PRA
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and #%00000111
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sta C3PO
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// Hide sprites; JiffyDOS timing regime is very strict, before transmitting
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// anything we need to make sure nothing will steal the cycles
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lda VIC_SPENA
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ldx #$00
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stx VIC_SPENA
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rts
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#endif // CONFIG_IEC_JIFFYDOS
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@@ -0,0 +1,33 @@
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//
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// JiffyDOS helper routine to wait for appropriate moment,
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// where no badline will interrupt the transmission
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//
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#if CONFIG_IEC_JIFFYDOS
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jiffydos_wait_line:
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lda VIC_SCROLY
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and #$10
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beq jiffydos_wait_line_done // screen is disabled, no need to watch for badlines
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// Avoid 2 lines before the badline, otherwise VIC will ruin the synchronization
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lda VIC_RASTER
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cmp #$2E
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bcc jiffydos_wait_line_done // we are safe, border - lot of time till badline
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!:
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lda VIC_RASTER // carry+ is definitely set here!
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sbc VIC_SCROLY
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and #$07 // we want 8 lowest bits
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cmp #$06
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bcs !-
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jiffydos_wait_line_done:
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rts
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#endif // CONFIG_IEC_JIFFYDOS
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