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some more bits for exotic hardware support

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FeralChild64 committed 2020-02-07 19:25:09 +01:00
1 parent 6a1070c8ac
commit 48b56968ed
10 files changed
+126 -4
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Makefile
+5 -2
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@@ -398,11 +398,14 @@ test_generic_x128: build/kernal_generic.rom build/basic_generic.rom build/symbol
test_testing: build/kernal_testing.rom build/basic_testing.rom build/symbols_testing.vs
x64 -kernal build/kernal_testing.rom -basic build/basic_testing.rom -moncommands build/symbols_testing.vs -1 $(TESTTAPE) -8 $(TESTDISK)
test_ultimate64: build/kernal_ultimate64.rom build/basic_ultimate64.rom build/symbols_ultimate64.vs
x64 -kernal build/kernal_ultimate64.rom -basic build/basic_ultimate64.rom -moncommands build/symbols_ultimate64.vs -1 $(TESTTAPE) -8 $(TESTDISK)
test_mega65: $(TARGET_M65_x)
../xemu/build/bin/xmega65.native -dmarev 2 -forcerom -loadrom $(TARGET_M65_x)
test_ultimate64: build/kernal_ultimate64.rom build/basic_ultimate64.rom build/symbols_ultimate64.vs
x64 -kernal build/kernal_ultimate64.rom -basic build/basic_ultimate64.rom -moncommands build/symbols_ultimate64.vs -1 $(TESTTAPE) -8 $(TESTDISK)
test_cx16: $(TARGET_X16_x)
../x16-emulator/x16emu -rom $(TARGET_X16_x)
test_hybrid: build/kernal_hybrid.rom build/symbols_hybrid.vs
@echo
c64/aliases/,aliases_hardware_cx16.s
+73
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@@ -0,0 +1,73 @@
//
// Names of hardware registers
//
#if CONFIG_PLATFORM_COMMANDER_X16
// VERA registers
.label __VERA_BASE = $9F20 // base address of the chip
.label VERA_ADDR_LO = $9F20
.label VERA_ADDR_MID = $9F21
.label VERA_ADDR_HI = $9F22
.label VERA_DATA0 = $9F23
.label VERA_DATA1 = $9F24
.label VERA_CTRL = $9F25
.label VERA_IEN = $9F26
.label VERA_ISR = $9F27
// VIA #1 registers
.label __VIA1_BASE = $9F60 // base address of the chip
.label VIA1_PRB = $9F60
.label VIA1_PRA = $9F61
.label VIA1_DDRB = $9F62
.label VIA1_DDRA = $9F63
.label VIA1_T1C_L = $9F64
.label VIA1_T1C_H = $9F65
.label VIA1_T1L_L = $9F66
.label VIA1_T1L_H = $9F67
.label VIA1_T2C_L = $9F68
.label VIA1_T2C_H = $9F69
.label VIA1_SR = $9F6A
.label VIA1_ACR = $9F6B
.label VIA1_PCR = $9F6C
.label VIA1_IFR = $9F6D
.label VIA1_IER = $9F6E
.label VIA1_PRA_NH = $9F6F
// VIA #2 registers
.label __VIA2_BASE = $9F70 // base address of the chip
.label VIA2_PRB = $9F70
.label VIA2_PRA = $9F71
.label VIA2_DDRB = $9F72
.label VIA2_DDRA = $9F73
.label VIA2_T1C_L = $9F74
.label VIA2_T1C_H = $9F75
.label VIA2_T1L_L = $9F76
.label VIA2_T1L_H = $9F77
.label VIA2_T2C_L = $9F78
.label VIA2_T2C_H = $9F79
.label VIA2_SR = $9F7A
.label VIA2_ACR = $9F7B
.label VIA2_PCR = $9F7C
.label VIA2_IFR = $9F7D
.label VIA2_IER = $9F7E
.label VIA2_PRA_NH = $9F7F
#endif
c64/aliases/,aliases_rom_cart.s
+5
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@@ -1,5 +1,10 @@
#if CONFIG_PLATFORM_COMMODORE_64
// Cartridge ROM locations
.label ICART_COLD_START = $8000 // $8000-$8001, cartridge cold start vector
.label ICART_WARM_START = $8002 // $8002-$8003, cartridge warm start vector (RESTORE key)
.label CART_SIG = $8004 // $8004-$8008, signature for cartridge detection
#endif
c64/basic/init/e394.basic_cold_start.s
+1 -1
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@@ -8,7 +8,7 @@
basic_cold_start:
#if !ROM_LAYOUT_M65 // can be safely skipped in Mega65 ROM layout
#if ROM_LAYOUT_STD // skip on non-sgtandard ROM layouts - they produce single image nevertheless
// Before doing anything, check if we have a compatible BASIC/KERNAL pair
c64/kernal/assets/cartridge_signature.s
+1
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@@ -1,4 +1,5 @@
// #LAYOUT# STD * #TAKE
// #LAYOUT# X16 * #IGNORE
// #LAYOUT# * KERNAL_0 #TAKE
// #LAYOUT# * * #IGNORE
c64/kernal/init/cartridge_check.s
+1
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@@ -1,4 +1,5 @@
// #LAYOUT# STD * #TAKE
// #LAYOUT# X16 * #IGNORE
// #LAYOUT# * KERNAL_0 #TAKE
// #LAYOUT# * * #IGNORE
c64/kernal/init/fce2.hw_entry_reset.s
+3 -1
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@@ -19,6 +19,8 @@ hw_entry_reset:
ldx #$FF
txs
#if CONFIG_PLATFORM_COMMODORE_64
// The following routine is based on reading the public KERNAL jumptable routine
// list, and making unimaginative assumptions about what should be done on reset.
// Also, https://codebase64.org/doku.php?id=base:assembling_your_own_cart_rom_image was used
@@ -30,10 +32,10 @@ hw_entry_reset:
jmp (ICART_COLD_START)
!:
#if CONFIG_PLATFORM_COMMODORE_64
// Disable the screen (and set 40 columns) to prevent visual glitches later
ldx #$28
stx VIC_SCROLX
#endif
// Initialising IO is obviously required. Also indicated by c64 prg p269.
c64/kernal/init/fd50.ramtas.s
+17
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@@ -49,6 +49,8 @@ RAMTAS:
ldx #>$033C
stx TAPE1+1
#if CONFIG_PLATFORM_COMMODORE_64
// Set screen address pointer ("Compute's Mapping the 64" p238)
// This is obvious boiler plate containing no creative input, but to avoid
// unnecessarily similarity to the C64 KERNAL, we use X instead of A to do this,
@@ -95,4 +97,19 @@ ramtas_32k:
ldy #$80
bne !- // branch always
#elif CONFIG_PLATFORM_COMMANDER_X16
ldx #>$0800
stx MEMSTR+1
ldy #$9F
sty MEMSIZK+1
#else
.error "Please fill-in RAMTAS"
#endif // platform
#endif // ROM layout
c64/kernal/interrupts/fe47.default_nmi_handler.s
+5
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@@ -17,10 +17,15 @@ default_nmi_handler:
// XXX confirm NMIs from CIA, or no other NMI will arrive!
#if CONFIG_PLATFORM_COMMODORE_64
jsr cartridge_check
bne !+
jmp (ICART_WARM_START)
!:
#endif
// According to C64 Wiki, if STOP key is pressed, the routine assumes warm start request
// XXX is it right? how to check that IRQ was caused by RESTORE?
c64/kernal/jumptable/fff3.jiobase.s
+15
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@@ -16,6 +16,21 @@
// As there is nothing between here and $FFFA, we can just hard code this in place.
// iobase: - commented out to prevent label naming conflict
#if CONFIG_PLATFORM_COMMODORE_64
ldy #$DC
ldx #$00
#elif CONFIG_PLATFORM_COMMANDER_X16
ldy #$9F
ldx #$60
#else
.error "Please fill-in IOBASE"
#endif
rts