all >3 length similarities explained, reworked via_vector to avoid accidental similarity, small project files fixes

.gitignore

@@ -7,6 +7,11 @@ temp.map
 ophis.bin
 build/*
 
+# Input to the similarity tool - copyrighted material, we can't check it in!
+
+basic
+kernal
+
 # Various IDE project files, temporary files, etc.
 
 *project

Makefile

@@ -143,6 +143,6 @@ testremote: build/newkern_generic build/newbasic_generic
 testm65: build/newc65
 	m65 -b ../mega65-core/bin/mega65r1.bit -k ../mega65-core/bin/KICKUP.M65 -R build/newc65 -4
 
-testsimilarity: build/newrom_generic src/similarity
+testsimilarity: build/newrom_generic $(TOOL_SIMILARITY)
 	$(TOOL_SIMILARITY) kernal build/newrom_generic
 	$(TOOL_SIMILARITY) basic build/newrom_generic

c64/basic/via_vector.s

@@ -2,39 +2,41 @@
 ;;
 ;; Helper routines for jumping via vectors, to be used with JSR
 ;;
+;; Note: they are not in the order of low memory vectors, to avoid
+;;       similarity with the original ROMs
 
-via_IOPEN:
-	jmp (IOPEN)
+via_ISAVE:
+	jmp (ISAVE)
+
+via_ILOAD:
+	jmp (ILOAD)
 
 via_ICLOSE:
 	jmp (ICLOSE)
 
+via_IOPEN:
+	jmp (IOPEN)
+
 via_ICHKIN:
 	jmp (ICHKIN)
 
-via_ICKOUT:
-	jmp (ICKOUT)
-
-via_ICLRCH:
-	jmp (ICLRCH)
-
 via_IBASIN:
 	jmp (IBASIN)
 
-via_IBSOUT:
-	jmp (IBSOUT)
-	
-via_ISTOP:
-	jmp (ISTOP)
-	
 via_IGETIN:
 	jmp (IGETIN)
-	
+
+via_ICKOUT:
+	jmp (ICKOUT)
+
+via_IBSOUT:
+	jmp (IBSOUT)
+
+via_ICLRCH:
+	jmp (ICLRCH)
+
 via_ICLALL:
 	jmp (ICLALL)
-	
-via_ILOAD:
-	jmp (ILOAD)
-	
-via_ISAVE:
-	jmp (ISAVE)
+
+via_ISTOP:
+	jmp (ISTOP)

strings/00003C

@@ -0,0 +1,3 @@
+$3C byte after some leading $00s
+
+Not creative. Not copyrightable.

strings/0002A2

@@ -0,0 +1,3 @@
+address $0200 + LDX# (argument does not match)
+
+Not even a full instruction - not copyrightable.

strings/002090FF

@@ -0,0 +1,3 @@
+$00 + JSR $FF90 (SETMSG)
+
+Instruction (jump to an official, docummented location) and some part. Not copyrightable.

strings/006020

@@ -0,0 +1,3 @@
+$00 + RTS (or instruction part) + JSR xxxx
+
+Single byte instruction with two halfs, or half of the instruction + half of other. Not copyrightable.

strings/00990001

@@ -0,0 +1,3 @@
+$00 + STA $0100, Y
+
+Single instruction and some part. Not copyrightable.

strings/00990002

@@ -0,0 +1,3 @@
+$00 + STA $0200, Y
+
+Single instruction and some part. Not copyrightable.

strings/00DD60AD00DD09

@@ -0,0 +1,5 @@
+address $DD00 (from previous instruction) + RTS (end of the routine, new one starting) + LDA $DD00 + ORA # (argument does not match)
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.

strings/026020

@@ -0,0 +1,3 @@
+byte $02 + RTS + JSR (address does not match) 
+
+One instruction + some fragments. Not copyrightable.

strings/02B96302

@@ -0,0 +1,4 @@
+$02 + LDA $0263, X (FAT table access)
+
+Single instruction (indexed access to a documented table) + some part. Not copyrightable.
+

strings/02B96D02

@@ -0,0 +1,3 @@
+$02 + LDA $026D, X (SAT table access)
+
+Single instruction (indexed access to a documented table) + some part. Not copyrightable.

strings/032060

@@ -0,0 +1,3 @@
+fragment + JSR + lower byte of jump address
+
+Not even a full instruction - not copyrightable.

strings/034C09

@@ -0,0 +1,3 @@
+fragment + JMP + lower byte of jump address
+
+Not even a full instruction - not copyrightable.

strings/034C33

@@ -0,0 +1,3 @@
+fragment + JMP + lower byte of jump address
+
+Not even a full instruction - not copyrightable.

strings/034C83

@@ -0,0 +1,3 @@
+fragment + JMP + lower byte of jump address
+
+Not even a full instruction - not copyrightable.

strings/034C9E

@@ -0,0 +1,3 @@
+fragment + JMP + lower byte of jump address
+
+Not even a full instruction - not copyrightable.

strings/034CFB

@@ -0,0 +1,3 @@
+fragment + JMP + lower byte of jump address
+
+Not even a full instruction - not copyrightable.

strings/034CFC

@@ -0,0 +1,3 @@
+fragment + JMP + lower byte of jump address
+
+Not even a full instruction - not copyrightable.

strings/036C1C036C

@@ -0,0 +1,3 @@
+$03 (most likely adddress higher byte) + JMP ($031C) (via public, documented vector) + JMP (address does not match)
+
+Code similarity due to Kernal API usage convention. Since 6510 CPU does not have indirect JSR, the only sane possibility to use Kernal API vectors in RAM ($0314-$0333) is to have JMP ($address) hardcoded somewhere. The jump table has intentionally strange order (to avoid code similarity as much as possible), but some small similarities can't be avoided in any reasonable way.

strings/036C1E036C

@@ -0,0 +1,3 @@
+$03 (most likely adddress higher byte) + JMP ($031E) (via public, documented vector) + JMP (address does not match)
+
+Code similarity due to Kernal API usage convention. Since 6510 CPU does not have indirect JSR, the only sane possibility to use Kernal API vectors in RAM ($0314-$0333) is to have JMP ($address) hardcoded somewhere. The jump table has intentionally strange order (to avoid code similarity as much as possible), but some small similarities can't be avoided in any reasonable way.

strings/036C20036C

@@ -0,0 +1,3 @@
+$03 (most likely adddress higher byte) + JMP ($0320) (via public, documented vector) + JMP (address does not match)
+
+Code similarity due to Kernal API usage convention. Since 6510 CPU does not have indirect JSR, the only sane possibility to use Kernal API vectors in RAM ($0314-$0333) is to have JMP ($address) hardcoded somewhere. The jump table has intentionally strange order (to avoid code similarity as much as possible), but some small similarities can't be avoided in any reasonable way.

strings/036C22036C

@@ -0,0 +1,3 @@
+$03 (most likely adddress higher byte) + JMP ($0322) (via public, documented vector) + JMP (address does not match)
+
+Code similarity due to Kernal API usage convention. Since 6510 CPU does not have indirect JSR, the only sane possibility to use Kernal API vectors in RAM ($0314-$0333) is to have JMP ($address) hardcoded somewhere. The jump table has intentionally strange order (to avoid code similarity as much as possible), but some small similarities can't be avoided in any reasonable way.

strings/036C24036C

@@ -0,0 +1,3 @@
+03 (most likely adddress higher byte) + JMP ($0324) (via public, documented vector) + JMP (address does not match)
+
+Code similarity due to Kernal API usage convention. Since 6510 CPU does not have indirect JSR, the only sane possibility to use Kernal API vectors in RAM ($0314-$0333) is to have JMP ($address) hardcoded somewhere. The jump table has intentionally strange order (to avoid code similarity as much as possible), but some small similarities can't be avoided in any reasonable way.

strings/036C2603

@@ -0,0 +1,3 @@
+$03 (most likely adddress higher byte) + JMP ($0326) (via public, documented vector)
+
+Code similarity due to Kernal API usage convention. Since 6510 CPU does not have indirect JSR, the only sane possibility to use Kernal API vectors in RAM ($0314-$0333) is to have JMP ($address) hardcoded somewhere. The jump table has intentionally strange order (to avoid code similarity as much as possible), but some small similarities can't be avoided in any reasonable way.

strings/036C2A036C

@@ -0,0 +1,4 @@
+$03 (most likely adddress higher byte) + JMP ($032A) (via public, documented vector) + JMP (address does not match)
+
+Code similarity due to Kernal API usage convention. Since 6510 CPU does not have indirect JSR, the only sane possibility to use Kernal API vectors in RAM ($0314-$0333) is to have JMP ($address) hardcoded somewhere. The jump table has intentionally strange order (to avoid code similarity as much as possible), but some small similarities can't be avoided in any reasonable way.
+

strings/036C2C03

@@ -0,0 +1,3 @@
+$03 (most likely adddress higher byte) + JMP ($032C) (via public, documented vector)
+
+Code similarity due to Kernal API usage convention. Since 6510 CPU does not have indirect JSR, the only sane possibility to use Kernal API vectors in RAM ($0314-$0333) is to have JMP ($address) hardcoded somewhere. The jump table has intentionally strange order (to avoid code similarity as much as possible), but some small similarities can't be avoided in any reasonable way.

strings/090185

@@ -0,0 +1,3 @@
+ORA #$01 (or part of another instruction) + STA (address does not match)
+
+At most one instruction and a half - not copyrightable.

strings/093020

@@ -0,0 +1,4 @@
+ORA #$30 + JSR without address
+alternatively a value (part of the instruction) followed by a conditional jump
+
+Instruction and a half. Not copyrightable.

strings/098085

@@ -0,0 +1,3 @@
+ORA #$80 (or part of another instruction) + STA (address does not match)
+
+At most one instruction and a half - not copyrightable.

strings/0A90034C

@@ -0,0 +1,4 @@
+$0A + BCC addr + JMP (address does not match)
+
+Some part + BCC / JMP combo (typical construction on a 6502, where there is no conditional far jump), even the address does not match. Not copyrightable.
+

strings/0D4C4F4144494E

@@ -0,0 +1,5 @@
+<RETURN> / last 'jsr printf' instruction byte (pure coincidence) + "LOADIN" PETSCII string
+
+Not copyrightable.
+
+

strings/0D534541524348494E47

@@ -0,0 +1,3 @@
+<RETURN> / last 'jsr printf' instruction byte (pure coincidence) + "SEARCHING" PETSCII string
+
+Not copyrightable.

strings/0D564552494659494E

@@ -0,0 +1,3 @@
+<RETURN> / last 'jsr printf' instruction byte (pure coincidence) + "VERIFYIN" PETSCII string
+
+Not copyrightable.

strings/108D00DD

@@ -0,0 +1,3 @@
+part of previous instruction + STA $DD00
+
+Instruction (storing register in a well-known I/O register) preceeded by a half of another one - not copyrightable.

strings/18607820

@@ -0,0 +1,3 @@
+CLC + RTS (end of subroutine, another one starts) + SEI + JSR (address does not match)
+
+Nothing creative here. First 2 instruction, which is are a common way to end a subroutine and indicate a success. Afterwards a start of new subroutine, which starts with disabling interrupts. Not copyrightable.

strings/1860A59D10

@@ -0,0 +1,3 @@
+CLC + RTS + LDA $9D + BPL
+
+Nothing creative here. First 2 instruction, which is are a common way to end a subroutine and indicate a success. Afterwards a start of new subroutine, which starts by checking a documented zeropage variable. Not copyrightable.

strings/2046524F4D20

@@ -0,0 +1,3 @@
+<SPACE> + FROM + <SPACE> - PETSCII string
+
+Not copyrightable.

strings/204F5045

@@ -0,0 +1,3 @@
+<SPACE> + OPE - PETSCII string
+
+Syllable starting a word is definitely not copyrightable.

strings/208EA6A9

@@ -0,0 +1,3 @@
+JSR $A68E + LDA # (value does not match)
+
+Instruction and a half. Not copyrightable.

strings/20BDFF20

@@ -0,0 +1,3 @@
+JSR $FFBD (SETNAM) + JSR (address does not match)
+
+Instruction (jump to official, documented location) + one byte of another one. Not copyrightable.

strings/29DF8D00DD

@@ -0,0 +1,3 @@
+AND #$DF + STA $DD00
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits. Here we just have a trivial bit manipulation - not creeative, not copyrightable.

strings/29DF8D00DD60AD00DD

@@ -0,0 +1,5 @@
+AND #$DF + STA $DD00 + RTS + LDA $DD00
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.

strings/29EF8D00DD60

@@ -0,0 +1,5 @@
+AND #$EF + STA $DD00 + RTS
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.

strings/29EF8D00DD60AD00DD09

@@ -0,0 +1,5 @@
+AND #$EF + STA $DD00 + RTS + LDA $DD00 + ORA#
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.

strings/29F78D00DD

@@ -0,0 +1,3 @@
+AND #$F7 + STA $DD00
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits. Here we just have a trivial bit manipulation - not creeative, not copyrightable.

strings/29F78D00DD60

@@ -0,0 +1,5 @@
+(beginning of the routine not matching) + AND #$F7 + STA $DD00 + RTS
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.

strings/386020

@@ -0,0 +1,3 @@
+SEC + RTS (end of subroutine, new one starts from the next byte) + JSR (address not matching)
+
+One subroutine ends with carry clear, second starts with JSR, but to a different address - accidental similarity, code most likely performs something different in both cases.

strings/3ED0034C37

@@ -0,0 +1,3 @@
+$3E + BNE addr + JMP $xx37
+
+Some part + BNE / JMP combo (typical construction on a 6502, where there is no conditional far jump), even the address does not fully match. Not copyrightable.

strings/4CBDFFA9

@@ -0,0 +1,3 @@
+JMP $FFBD (SETNAM) + LDA #$ (value does not match)
+
+Instruction (jump to an official, documented location) + opcode of another one. Not copyrightable.

strings/4F5045

@@ -0,0 +1,3 @@
+ORE - PETSCII string
+
+Not copyrightable.

strings/524F4D

@@ -0,0 +1,3 @@
+ROM - PETSCII string
+
+Not copyrightable.

strings/564552

@@ -0,0 +1,3 @@
+VER - PETSCII string
+
+Not copyrightable.

strings/5645524946

@@ -0,0 +1,3 @@
+VERIF - PETSCII string, part of 'VERIFY'
+
+Not copyrightable.

strings/5902D0F8

@@ -0,0 +1,3 @@
+$0259 (LAT table address) + BNE $F8 (few bytes back)
+
+Instruction + some parts (revealing that this is some manipulation on documented Kernal table). Not copyrightable.

strings/6031EA

@@ -0,0 +1,3 @@
+RTS (ending a subroutine, new one starts) + conditional jump
+
+Nothing creative here - not copyrightable.

strings/60A59D10

@@ -0,0 +1,3 @@
+RTS (belonging to previopus subroutine) + LDA $9D (MSGFLG) + BPL
+
+The only similarity here is, that the subroutine starts by checking a documented variable. Not copyrightable.

strings/60A59D10FB

@@ -0,0 +1,3 @@
+RTS + LDA $9D (MSGFLG) + BPL $FB
+
+Check documented variable value, utilize nearest RTS (a very common optimization, mentionedd for example here just few days ago: https://gitlab.com/mkslack/Area6510/commit/9bdc624574c76661db302cdbf85559fb0e9e309a) to quit subroutine if the highest bit is not 1 (the easiest way to distinguish 2 documented values of the MSGFLG: $00 and $80). Nothing creative here - not copyrightable.

strings/60AD00DD0910

@@ -0,0 +1,5 @@
+RTS (end of the routine, new one starting) + LDA $DD00 + ORA #$10
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.

strings/60AD00DD09108D00DD

@@ -0,0 +1,5 @@
+RTS (end of the routine, new one starting) + LDA $DD00 + ORA #$10 + STA $DD00
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.

strings/630285

@@ -0,0 +1,3 @@
+address $0263 + STA (address does not match)
+
+Not even a full instruction. Not copyrightable.

strings/686020

@@ -0,0 +1,3 @@
+PLA + RTS (end of subroutine, another one starting) + JSR (address does not match)
+
+End of a routine preserving .A register + part of instruction belonging to another subroutine. Not copyrightable.

strings/6C1A036C

@@ -0,0 +1,3 @@
+JMP ($031A) (via public, documented vector) + JMP (address does not match)
+
+Code similarity due to Kernal API usage convention. Since 6510 CPU does not have indirect JSR, the only sane possibility to use Kernal API vectors in RAM ($0314-$0333) is to have JMP ($address) hardcoded somewhere. The jump table has intentionally strange order (to avoid code similarity as much as possible), but some small similarities can't be avoided in any reasonable way.

strings/7AD0034C

@@ -0,0 +1,3 @@
+$7A + BNE with matching address + JMP
+
+Single instruction + some matching parts of two others. Not copyrightable.

strings/9914038810

@@ -0,0 +1,3 @@
+STA $0314, Y + DEY + BPL addr
+
+Part of memory copy routine to set/initialize vector table in RAM (a documented one). There is a limited amount of sane ways to implement this code - ours is clearly different from the original, or there would be more similarities. Such a small fragment of rather common routine is definitely not copyrightable.

strings/A000B17AD0

@@ -0,0 +1,3 @@
+LDY #$00 + LDA ($7A), Y + BNE (offset does not match)
+
+Small part of a loop processing data pointed by TEXTPTR - not creative, not copyrightable.

strings/A59AC903

@@ -0,0 +1,3 @@
+LDA $9A (DFLTO) + CMP #$03
+
+Check whether the default output device is screen - not even fully matching the original ROM (different branch instruction used) - might be one onstruction on other architecture. Not copyrightable.

strings/A5BAC902D0

@@ -0,0 +1,3 @@
+LDA $BA + CMP #$02 + BNE (offset does not match)
+
+Check whether the current device number is 2 (RS-232). Not creative - not copyrightablee.

strings/A67AA47B

@@ -0,0 +1,5 @@
+LDX $7A + LDY $7B
+
+Loading TXTPTR value to X/Y registers, would be 1 instruction on any 16-bit CPU. Not creative - not copyrightable.
+
+

strings/A90020BDFF

@@ -0,0 +1,4 @@
+LDA #$00 + JSR $FFBD (SETNAM routine)
+
+Code to set the file name as empty ($FFBD is a standard, documented address). Trivial - not copyrightable.
+

strings/A90020BDFF20

@@ -0,0 +1,3 @@
+LDA #$00 + JSR $FFBD (SETNAM routine) + JSR (address differs)
+
+Code to set the file name as empty ($FFBD is a standard, documented address), followed by jump to subroutine (but placed elsewere). Trivial - not copyrightable.

strings/A9009900

@@ -0,0 +1,3 @@
+LDA #$00 + STA xx00, Y
+
+Instruction and a half (probably a loop zeroing something - but something different in both cases). Not copyrightable.

strings/B190034C

@@ -0,0 +1,3 @@
+LDA ($0390), Y + JMP (address does not match)
+
+Instruction and a half - not copyrightable.

strings/B1B0034C

@@ -0,0 +1,3 @@
+LDA ($03B0), Y + JMP (address does not match)
+
+Instruction and a half - not copyrightable.

strings/BAA90085

@@ -0,0 +1,3 @@
+$BA + LDA #$00 + STA (address does not match)
+
+One full instruction (loading acumulator with 0) and some parts - not copyrightable.

strings/C8B17AF0

@@ -0,0 +1,3 @@
+INY + LDA ($7A),Y + BEQ (offset does not match)
+
+Small part of a loop processing data pointed by TEXTPTR - not creative, not copyrightable.

strings/C8C4B7

@@ -0,0 +1,3 @@
+INY + CPY $B7 (FNLEN documented variable)
+
+Tiny part of the loop processing file name or IEC command. Not creative - not copyrightable.

strings/D0034C37

@@ -0,0 +1,3 @@
+BNE $03 + JMP xx37
+
+Instruction and a half - part of a common workaround for conditional jumps not reaching far. Not copyrightable.

strings/DD09108D00DD

@@ -0,0 +1,5 @@
+$DD + ORA #$10 + STA $DD00
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.

strings/DD29DF8D00DD60AD00DD

@@ -0,0 +1,5 @@
+$DD + AND #$DF + STA $DD00 + RTS (end of the routine, new one starting) + LDA $DD00
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.

strings/DD29DF8D00DD60AD00DD09208D00DD

@@ -0,0 +1,5 @@
+$DD + AND #$DF + STA $DD00 + RTS (end of the routine, new one starting) + LDA $DD00 + ORA #$20 + STA $DD00
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.

strings/DD29EF8D00DD

@@ -0,0 +1,5 @@
+$DD + AND #$EF + STA $DD00
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.

strings/DD29EF8D00DD60

@@ -0,0 +1,5 @@
+$DD + AND #$EF + STA $DD00 + RTS
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.

strings/DD29EF8D00DD60AD00DD09

@@ -0,0 +1,5 @@
+$DD + AND #$EF + STA $DD00 + RTS + LDA #$DD00 + ORA # (argument does not match)
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.

strings/DD29F78D00DD60

@@ -0,0 +1,5 @@
+$DD + AND #$F7 + STA $DD00 + RTS
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.

strings/DD60AD00DD09208D00DD

@@ -0,0 +1,5 @@
+$DD + RTS (end of the routine, new one starting) + LDA $DD00 + ORA #$20 + STA $DD00
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.

strings/DF8D00DD

@@ -0,0 +1,3 @@
+$EF + STA $DD00
+
+Instruction (storing acumulator in a documented I/O register) and some part. Not copyrightable.

strings/DF8D00DD60AD00DD

@@ -0,0 +1,5 @@
+$DF + STA $DD00 + RTS + LDA $DD00
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.

strings/E5C91DD0

@@ -0,0 +1,3 @@
+$E5 + CMP #$1D + BNE (offset does not match)
+
+Instruction + some parts. Not copyrightable.

strings/EF8D00DD60AD00DD09

@@ -0,0 +1,5 @@
+$EF + STA $DD00 + RTS + LDA $DD00 + ORA # (value does not match)
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.

strings/F6A90085

@@ -0,0 +1,3 @@
+$F6 + LDA #$00 + STA ...
+
+A part + instruction to clear the accumulator + opcode of another instruction. Not copyrightable.

strings/F78D00DD60

@@ -0,0 +1,5 @@
+$F7 + STA $DD00 + RTS
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.