all >3 length similarities explained, reworked via_vector to avoid accidental similarity, small project files fixes

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FeralChild64 committed 2019-08-03 22:02:56 +02:00
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CLC + RTS (end of subroutine, another one starts) + SEI + JSR (address does not match)
Nothing creative here. First 2 instruction, which is are a common way to end a subroutine and indicate a success. Afterwards a start of new subroutine, which starts with disabling interrupts. Not copyrightable.