explained all similarities >3, some minor cleanups

c64/aliases/,aliases_ram_lowmem.s

@@ -159,7 +159,7 @@
 	.label SAT       = $26D  // $26D-$276, secondary addresses  (table, 10 bytes)
 	.label KEYD      = $277  // $277-$280, keyboard buffer
 	.label MEMSTR    = $281  // $281-$282, start of BASIC memory
-	.label MEMEND    = $283  // $283-$284, NOTE: Mapping the 64 erroneously has the hex as $282 (DEC is correct), name seems to be mistaken too
+	.label MEMSIZK   = $283  // $283-$284, NOTE: Mapping the 64 erroneously has the hex as $282 (DEC is correct)
 	.label TIMOUT    = $285  //            IEEE-488 timeout
 	.label COLOR     = $286  //            current text foreground color
 	.label GDCOL     = $287  //            color of character under cursor

c64/kernal/memtop.s

@@ -12,13 +12,13 @@ MEMTOP:
 
 	bcc memtop_set
 	
-	ldy MEMEND+1
-	ldx MEMEND+0
+	ldy MEMSIZK+1
+	ldx MEMSIZK+0
 	rts
 
 memtop_set:
 
-	sty MEMEND+1
-	stx MEMEND+0
+	sty MEMSIZK+1
+	stx MEMSIZK+0
 	
 	rts

c64/kernal/ramtas.s

@@ -61,14 +61,14 @@ ramtas_l2:
 	ldx #>$0400
 	stx HIBASE
 	
-	//  Work out RAM size and put in MEMSTR and MEMEND
+	//  Work out RAM size and put in MEMSTR and MEMSIZK
 	// "Compute's Mapping the 64", p54
 	//  http://unusedino.de/ec64/technical/project64/mapping_c64.html
 	ldx #>$0800
 	stx MEMSTR+1
 	ldx #$00
 	stx MEMSTR+0
-	stx MEMEND+0
+	stx MEMSIZK+0
 	// Try to modify $8000, if it fails then RAM ends at $7FFF, else $9FFF
 	lda $8000
 	eor #$FF
@@ -79,12 +79,12 @@ ramtas_l2:
 	beq ramtas_32K_RAM
 	sta $8000
 	ldx #$A0
-	stx MEMEND+1
+	stx MEMSIZK+1
 	jmp ramtas_RAM_sized
 ramtas_32K_RAM:	
 	sta $8000 		// in case RAM is hiding beneath a ROM
 	ldx #$80
-	stx MEMEND+1
+	stx MEMSIZK+1
 	// Fall through
 ramtas_RAM_sized:	
 	

src/build_segment.cc

@@ -316,7 +316,7 @@ void calcRoutineSizes()
     // during this pass,  which would otherwise upset things later
 
     outFile << "\n" << ".segment " << CMD_segName << " [start=$100, min=$100, max=$FFFF]" << "\n";
-    outFile << "#define BUILD_" << CMD_segName << "\n";
+    outFile << "#define SEGMENT_" << CMD_segName << "\n";
 
     for (const auto &sourceFile : GLOBAL_sourceFiles)
     {
@@ -516,7 +516,7 @@ void compileSegment()
                ", max=$" << std::hex << CMD_hiAddress <<
                ", outBin=\"" << CMD_outFile << "\", fill]" <<
                "\n";
-    outFile << "#define BUILD_" << CMD_segName << "\n";
+    outFile << "#define SEGMENT_" << CMD_segName << "\n";
 
     // Write files which only contain definitions (no routines)
 
@@ -609,6 +609,7 @@ SourceFile::SourceFile(const std::string &fileName, const std::string &dirName)
     inFile.seekg(0);
     inFile.read(&content[0], fileLength);
     if (!inFile.good()) ERROR("error reading file content");
+    if (content.back() != '\n') content.push_back('\n');
 
     inFile.close();
 
@@ -915,7 +916,14 @@ int KS(const std::vector<SourceFile *> &routines,
     int n, int C,
     std::list<bool> &solution) // sequence of decisions for each routine, has to be empty when calling
 {
-    // This routine solves a knapsack problem using a dynamic programming
+    // This routine solves a knapsack problem using a dynamic programming.
+    //
+    // In short: 'routines' contains a list of routines that can potentially be placed in the gap of size C.
+    // We start from index n (the highest one), referencing the last routine from the list (the largest one,
+    // as the list is sorted). Our goal: by recursively searching the tree of all possible solutions
+    // (solution = a sequence of decisions, each telling whether to take the routine or not) find the one
+    // that fills the gap in the most complete way. Additional cache greatly speeds up the algorithm.
+    // See the comments below to fully understand how it works.
 
     // XXX Possible efficiency improvement for the future: try to consider more than one gap at once,
     //     this will need a serious rework of the dynamic cache handling and will probably hurt the performance

strings/0020BDFF

@@ -0,0 +1,4 @@
+$00 + JSR $FFBD (SETNAM routine jumptable address)
+
+Value + a jump to a documented location - trivial, not copyrightable.
+

strings/0020BDFF20

@@ -0,0 +1,3 @@
+$00 + JSR $FFBD (SETNAM routine jumptable address) + JSR (address does not match)
+
+Value + a jump to a documented location + beginning of the next instruction - trivial, not copyrightable.

strings/00857B60

@@ -0,0 +1,3 @@
+$00 + STA $7B + RTS
+
+Routine ending, storing a value in a documented zeropage location - trivial, not copyrightable.

strings/00DD0910

@@ -0,0 +1,7 @@
+$DD00 + ORA #$10
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions. What's more - this is only an instruction and a half - trivial, not copyrightable.
+
+

strings/00DD09108D00DD

@@ -0,0 +1,5 @@
+$DD00 + ORA #$10 + STA $DD00
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.

strings/00DD29DF8D00DD

@@ -0,0 +1,6 @@
+$DD00 + AND #$DF + STA $DD00
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.
+

strings/00DD29F78D00DD

@@ -0,0 +1,6 @@
+$DD00 + AND #$F7 + STA $DD00
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.
+

strings/00DD60AD00DD0910

@@ -0,0 +1,6 @@
+$DD00 + RTS + LDA $DD00 + ORA #$10
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.
+

strings/01857AA5

@@ -0,0 +1,3 @@
+$01 + STA $7A + LDA (address does not match)
+
+Instruction (storing value on zero page) + some parts - trivial, not copyrightable.

strings/02186020

@@ -0,0 +1,4 @@
+$02 + CLC + RTS + JSR (address does not match)
+
+Subroutine ending by setting 'carry' flag (standard way to indicate failure) placed
+just before another one, starting with a jump (to a different address) - not creative, not copyrightable.

strings/034C28

@@ -0,0 +1,3 @@
+$03 + JMP (address matches only partially)
+
+Not even a full instruction - not copyrightable.

strings/034CE1

@@ -0,0 +1,3 @@
+$03 + JMP (address match only partially)
+
+Not even a full instruction - not copyrightable

strings/0DDC68A868AA6840

@@ -0,0 +1,7 @@
+$DC0D + PLA + TAY + PLA + TAX + PLA + RTI
+
+Some access to a docummented hardware register (but details differ) + return from the interrupt in a standard 6502 way - see for example here:
+
+http://6502.org/tutorials/register_preservation.html
+
+Not copyrightable.

strings/1860AD00DD

@@ -0,0 +1,3 @@
+CLC + RTS + LDA $DD00
+
+End of a routine setting carry flag as a result (probably to indicate error) followed by another, which starts by reading a documented hardware register. Not creative (especially that routine location is determineed by algorithm in our case) - not copyrightable.

strings/290FF023

@@ -0,0 +1,3 @@
+AND #$0F + BEQ (offset match)
+
+Check whether the lowest nibble of a byte is zero or not - trivial, not copyrightable.

strings/29DF8D00DD60

@@ -0,0 +1,5 @@
+AND #$DF + STA $DD00 + RTS
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.

strings/3020D2FF68

@@ -0,0 +1,3 @@
+$30 + JSR $FFD2 + PLA
+
+A byte, call to a documented routine (CHROUT), restoring the register value - trivial, not copyyrightable.

strings/31EA66FE47FE4AF391F20EF250F233F357F1CAF1EDF63EF12FF366FEA5F4EDF5

@@ -0,0 +1,6 @@
+a list of vectors to be copied starting from $0314
+
+Values of the vectors are already present in many autostart software - as it often overrides them,
+sometimes changing one to trigger autostart (one of the possible techniques). We have to use the same
+vector values to be compatible (in fact, it even complicates our implementation) - see *.interop files
+for more details.

strings/60A000A2

@@ -0,0 +1,3 @@
+RTS (end of previous routine) + LDY #$00 + LDX (value does not match)
+
+Routine starts by loading 0 to Y and something (here values differ) to X - trivial, not copyrightable.

strings/60AD00DD09208D00DD

@@ -0,0 +1,7 @@
+RTS + LDA $DD00 + ORA #$20 + STA $DD00
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.
+
+

strings/6900852E

@@ -0,0 +1,5 @@
+ADC #$00 + STA $2E ($2D-$2E is VARTAB, end of BASIC code)
+
+Part of code incrementing a documented 16-bit value - trivial, not copyrightable.
+
+

strings/7060A5

@@ -0,0 +1,3 @@
+$70 + RTS + LDA (zeropage address, but does not match)
+
+One instruction (and just a one-byte instruction) + some parts - not copyrightable.

strings/85D4A922

@@ -0,0 +1,3 @@
+STA $D4 + LDA #$22
+
+Storing value to a well-known zeropage variable + loading another to the accumulator - not crative, not copyrightable.

strings/8D00DD60AD00DD

@@ -0,0 +1,5 @@
+STA $DD00 + RTS + LDA $DD00
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.

strings/8D00DD60AD00DD29

@@ -0,0 +1,5 @@
+STA $DD00 + RTS + LDA $DD00 + AND (value does not match)
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.

strings/8D850260

@@ -0,0 +1,5 @@
+STA $0285 (TIMOUT variable) + RTS
+
+SETTMO routine. There really is just one sane way to implement
+a subroutine storing accumulator in a fixed memory location.
+Not creative - not copyrightable.

strings/A8AD0002

@@ -0,0 +1,3 @@
+$A8 + LDA $0200
+
+Instruction (accessing BASIC instruction buffer) + some part. Trivial, not copyrightable.

strings/A9006020

@@ -0,0 +1,3 @@
+LDA #$00 + RTS + JSR (address does not match)
+
+End of a rutine which returns 0 in accumulator, another one starts with a jump (but to a different address) - trivial, not copyrightable.

strings/AD00DD29

@@ -0,0 +1,7 @@
+LDA $DD00 + AND (value does not match)
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions. Also - instruction and a half is trivial - not copyrightable.
+
+

strings/AD00DD29F78D00DD

@@ -0,0 +1,6 @@
+LDA $DD00 + AND #$F7 + STA $DD00
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.
+

strings/AD00DD29F78D00DD60

@@ -0,0 +1,6 @@
+LDA $DD00 + AND #$F7 + STA $DD00 + RTS
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+
+

strings/C3C2CD3830

@@ -0,0 +1,15 @@
+CBM80 PETSCII string
+
+CBM80 is the string used to compare with the signature block of
+a cartridge. It is required for interoperability with C64 cartridges,
+and the requirement for this string is explicit, and is well documented,
+including the string itself, in many places, such as:
+
+http://mirror.thelifeofkenneth.com/sites/remotecpu.com/Commodore/Reference%20Material/Manuals/Hardware%20Manuals/Datel%20Eprommer64%20Instruction%20Manual.pdf
+
+Indeed, the C64 Programmer's Reference Guide describes it on p263.
+
+Since Commodore instructed cartridge developers to include the string
+in cartridges, it cannot be held to be a violation of copyrights,
+even if it were able to be copyrighted, which we do not accept on grounds
+including that it is a list of facts (published by Commodore themselves)

strings/C8B17A

@@ -0,0 +1,4 @@
+INY + LDA ($7A),Y
+
+Part of the loop reading BASIC statement, loops reading data block pointed by vector
+always look like this on 6502, as LDA (...),X does not exists on this CPU. Trivial - not copyrightable.

strings/C922D00B

@@ -0,0 +1,3 @@
+CMP #$22 + BNE (offset matches)
+
+Comparing register to value, would be a single instruction on other architectures. Trivial - not copyrightable.

strings/DF8D00DD60AD00DD09208D00DD

@@ -0,0 +1,7 @@
+$DF + STA $DD00 + RTS + LDA $DD00 + ORA #$20 + STA $DD00
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.
+
+

strings/E6C90DD0

@@ -0,0 +1,3 @@
+$E6 + CMP #$0D + BNE (offset does not match)
+
+Instruction + some parts. Not copyyrightable.

strings/EF8D00DD

@@ -0,0 +1,5 @@
+$EF + STA $DD00
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.

strings/EF8D00DD60

@@ -0,0 +1,6 @@
+$EF + STA $DD00 + RTS
+
+$DD00 is a hardware register, where one typically set/unset/read individual bits.
+Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
+Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.
+

strings/F6A5BA20

@@ -0,0 +1,3 @@
+$F6 + LDA $BA + JSR (address does not match)
+
+One instruction (reading a well-known zeropage value) + some parts. Not copyrightable.

strings/FD4C15FD4C1AFD4C

@@ -0,0 +1 @@
+This is a part of Kernal jumptable - series of jumps, sometimes to the well known addreses (or through documented vectors). No business logic, part of the Kernal API itself (has to be as it is to maintain compatibility) - not copyrightable.