explained similarities >3, some documentation update
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@@ -1,7 +1,14 @@
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# OpenROMs development guide
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Note: preliminary version, incomplete!
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NOTE: this document is a preliminary version, definitely incomplete!
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## In-depth protocol description
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- [JiffyDOS](./Protocol-JiffyDOS.md)
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- [DolphinDOS](./Protocol-DolphinDOS.md)
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## Guidelines for software developers for OpenROMs compatibility
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@@ -28,17 +35,17 @@ OpenROMs interrupt handlers do not touch the ROM mapping, range `0x4000-0xBFFF`
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OpenROMs provides support for several additional PETSCII codes (all compatible with C128 and/or C65):
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| PETSCII | description |
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|:-------:|:---------------------------------------------------:|
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| `$07` | bell (C128 and C65 compatible), not implemented yet |
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| `$1B` | `ESC` key (C128 and C65 compatible) |
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| `$84` | `HELP` key (C128 and C65 compatible) |
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| `$10` | `F9` key (C65 compatible) |
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| `$15` | `F10` key (C65 compatible) |
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| `$16` | `F11` key (C65 compatible) |
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| `$17` | `F12` key (C65 compatible) |
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| `$19` | `F13` key (C65 compatible) |
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| `$1A` | `F14` key (C65 compatible) |
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| PETSCII code | description |
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| :----------: | :-------------------------------------------------- |
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| `$07` | bell (C128 and C65 compatible), not implemented yet |
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| `$1B` | `ESC` key (C128 and C65 compatible) |
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| `$84` | `HELP` key (C128 and C65 compatible) |
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| `$10` | `F9` key (C65 compatible) |
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| `$15` | `F10` key (C65 compatible) |
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| `$16` | `F11` key (C65 compatible) |
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| `$17` | `F12` key (C65 compatible) |
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| `$19` | `F13` key (C65 compatible) |
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| `$1A` | `F14` key (C65 compatible) |
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There is no official PETSCII code for `TAB` - we can't utilize the ones from C128 or C65 because it conflicts with some C64 codes.
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@@ -46,9 +53,9 @@ There is no official PETSCII code for `TAB` - we can't utilize the ones from C12
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`SHFLAG` (`$028D`) variable is extended to support additional bucky keys on C128 and C65 keyboards:
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| bits 7-5 | bit 4 | bit 3 | bit 2 | bit 1 | bit 0 |
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|:--------:|:-----------:|:-----:|:-----: |:--------:|:-------:|
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| reserved | `CAPS LOCK` | `ALT` | `CTRL` | `VENDOR` | `SHIFT` |
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| bits 7-5 | bit 4 | bit 3 | bit 2 | bit 1 | bit 0 |
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| :------: | :---------: | :------: | :------: | :------: | :------: |
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| reserved | `CAPS LOCK` | `ALT` | `CTRL` | `VENDOR` | `SHIFT` |
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Bits 3 and 4 are extension to the original variable, compatible with the C128 ROMs API. There is no official way to retrieve `NO_SCRL` status as of yet. The `40/80` key status cannot be retrieved in C64 mode at all (C128 hardware limitation).
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@@ -61,8 +68,8 @@ Make sure to read the main [README](../README.md) first - although any help with
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List of the most important make targets:
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| target | meaning |
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|:-------------------:|:------------------------------------------------------------------------------:|
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| target | description |
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| :------------------ | :----------------------------------------------------------------------------- |
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| `all` | builds all ROMs, places them in 'build' subdirectory |
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| `clean` | removes all the compilation results and intermediate files |
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| `updatebin` | upates ROMs in 'bin' subdirectory - with embedded version string, for release |
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@@ -80,7 +87,7 @@ List of the most important make targets:
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Currently there are 2 ROM layouts defined:
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- `STD` - with 2 code segments: `BASIC` (`$A000-$E4D2`, where `$C000-$DFFF` is a skip-gap for RAM and I/O) and `KERNAL` (`$E4D2 - $FFFF`)
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- `STD` - with 2 code segments: `BASIC` (`$A000-$E4D2`, where `$C000-$DFFF` is a skip-gap for RAM and I/O area) and `KERNAL` (`$E4D3 - $FFFF`)
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- `M65` - where `BASIC` becames `BASIC_0` and `KERNAL` becames `KERNAL_0`, additional segments might be added to the build system in the future; at the moment of writing this document additional 8KB of ROM is defined as `KERNAL_1` segment
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To check for current ROM layout or code segment use KickAssembler preprocessor defines, like `ROM_LAYOUT_STD`, `ROM_LAYOUT_M65`, `SEGMENT_BASIC`, `SEGMENT_KERNAL_1`.
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@@ -110,7 +117,7 @@ where:
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- `<code-segment>` - `KERNAL`, `BASIC`, `KERNAL_0`, `KERNAL_1`, etc., asterisk symbol can be used to match any segment
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- `<action>` - what to do when layout and segment match:
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| action | meaning |
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| action | description |
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| :------------ | :-------------------------------------------- |
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| `#IGNORE` | ignore the file completely |
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| `#TAKE` | compile the file normally |
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@@ -0,0 +1,3 @@
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$03 + JSR $E8EA
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Instruction (calling a well-known subroutine for screen line scrolling) + some part. Trivial, not copyrightable.
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@@ -0,0 +1,3 @@
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$03 + JMP$xx13
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Not even a full instruction. Trivial - not coprightable.
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@@ -0,0 +1,3 @@
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$03 + LDA #$00 + STA (zeropage address does not match)
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Instruction (loading 0 to accumulator) + some parts. Trivial - not copyrightable.
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@@ -0,0 +1,3 @@
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$18 + JSR $E9FF
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Call to a well-known routine + some part. Trivial - not copyrightable.
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@@ -0,0 +1,3 @@
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AND #$02 + BNE (offset matches)
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Check for some bits in the accumulator. Trivial - not copyrightable.
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@@ -0,0 +1,3 @@
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PHA + LDA $AD + PHA + LDA (zeropage address does not match)
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Part of the instruction sequence restoring a well-known 16-bit zeropage variable from a stack. Trivial - not copyrightable.
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@@ -0,0 +1,3 @@
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PHA + LDA $AE + PHA
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Retrievin some data from the stack, among them matching zeropage variable. Trivial - not copyyrightable.
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PHA + LDA $AE + PHA + LDA (zeropage address does not match)
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Part of the instruction sequence restoring a well-known 16-bit zeropage variable from a stack. Trivial - not copyrightable.
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@@ -0,0 +1,3 @@
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PHA + STA $AD + PHA + STA (zeropage address does not match)
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Part of the instruction sequence storing a well-known 16-bit zeropage variable on a stack. Trivial - not copyrightable.
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@@ -0,0 +1,3 @@
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PHA + STA $AE + PHA + STA (zeropage address does not match)
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Part of the instruction sequence storing a well-known 16-bit zeropage variable on a stack. Trivial - not copyrightable.
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@@ -0,0 +1,3 @@
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SEI + LDA #$00 + STA (zeropage address does not match)
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Disable interrupts, store 0 in some memoryy location (address does not match). Trivial and not creative - not copyrightable.
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STY $D3 + JMP (address does not match)
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Instruction (storing data in a well-known memory location) + some part. Trivial - not copyrightable.
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STX $D6 + JSR $E56C + LDY (zeropage address deos not match)
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Update one screen-related value with coontent of X register, call a well-known routine to adjust remaining ones - trivial, not copyrightable.
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$0288 + STA $AD
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Instruction + some part (address of a documented variable). Trivial - not copyrioghtable.
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TXA + PHA + LDA #$01
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Store .X register on the stack (would be a single instruction on 65C02) + loading accumulator with 1. Trivial and not creative - not copyrightable.
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TYA + PHA + TXA + PHA
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Store Y and X CPU registers on a stack (would be only 2 instruction on 65C02 and above). Trivial - not copyrightable.
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LDY #$00 + TYA + STA ($2B),Y
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6502 way to store 0 in a memory location pointed by a well-known pointer. Trivial - not copyrightable.
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LDY #$02 + LDA #$00 + STA (address does not match)
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Put $02 to Y register, put 0 into accumulator and store it somewhere (address does not match) - trivial, not copyrightable.
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LDY #$27 + LDA ($AC),Y + STA (zeroopage address deos not match),Y
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Get the last character from the screen line (using a documented vector) and store it somewhere (details differ here). Trivial - not copyrightable.
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LDY #$E4 + JSR $AB1E
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Print a string by calling a well-known routine, only part of the string address matches. Trivial - not copyrightable.
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LDX #$18 + JSR $E9FF
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Clear the last screen line by calling a well-known routine. Trivial - not copyrightable.
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@@ -0,0 +1,3 @@
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LDX #$18 + JSR $E9FF + DEX + BPL (go back to JSR)
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Clear the whole screen by repeatedly calling a well-known routine to clear a single line. Not creative - not copyrightable.
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LDA $AC + PHA + LDA (zeropage address does not match)
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Storing some data on a stack, among them the same zeropage variable - trivial, not copyrightable.
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LDA #$01 + BIT (to skip next instruction) + LDA # (value does not match)
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Setting accumulator to $01 or some other value (not included in similarity) depending on some condition (also not included in the similarity). Trivial - not copyrightable.
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@@ -0,0 +1,3 @@
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LDA #$01 + BIT (skip next instruction) + LDA #$00
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Part of code setting accumulator to 0 or 1 depending on some condition (check not included in similarity). Trivial - not copyrightable.
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LDA #$20 + STA ($D1),Y + DEY + BPL (offset does not match)
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Part of the loop filling area of the screen with spaces. Not creative - not coprightable.
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TAX + PLA + TAY
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Simple register manipulation to retrieve .Y from the stack without losing .A. Trivial - not copyrightable.
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TAX + PLA + TAY + LDA (zeropage address does not match)
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Some simple stack/register data transfer + loading accumulator from memory (address does not match) - trivial. Not copyrightable.
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$C3 + STA $AE + LDA (zeropage adddress does not match)
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Instruction + some parts. Trivial - noot copyrightable.
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INY + LDA ($D1),Y + DEY + STA ($D1),Y + INY
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Part of the loop moving some memory content (pointed by a zeropage variable) by 1 byte. Not creative - not copyrightable.
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INY + LDA ($F3),Y + DEY + STA ($F3),Y + INY
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Part of the loop moving some memory content (pointed by a zeropage variable) by 1 byte. Not creative - not copyrightable.
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BNE (offset matches) + LDA #$80 + STA (zeropage address does not match)
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Depending on some condition (check does not fully match) store $80 in some memoryy location (address does not match). Trivial - not copyrightable.
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$E4 + JSR $AB1E
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Call to a well-known routine + some part. Trivial - not copyrightable.
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$EA + LDA $01 + AND #$10
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Clearing bit on bte fetched from a documented hardware port + some part of other instruction. Trivial - not copyyrightable.
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$EC + CLC + RTS (end of routine) + JSR (address does not match)
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Routine ending with enabling interrupts + beginning of another one (just instruction opcode matches, not the argument). Trivial - not copyrightable.
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$FF + JSR$xx06
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Not even a full instruction. Trivial - not copyrightable.
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