fixes for IEC
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@@ -0,0 +1,7 @@
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iec_pull_data_release_atn_clock:
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lda CI2PRA
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ora #BIT_CI2PRA_DAT_OUT ; pull
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and #$FF - BIT_CI2PRA_ATN_OUT - BIT_CI2PRA_CLK_OUT ; release
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sta CI2PRA
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rts
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+83
-98
@@ -1,118 +1,103 @@
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;; Receive a byte from the IEC bus.
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;; reference http://www.zimmers.net/anonftp/pub/cbm/programming/serial-bus.pdf
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;; page 11.
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;; XXX rework this, according to pagetable.com
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;; Implemented based on https://www.pagetable.com/?p=1135, https://github.com/mist64/cbmbus_doc,
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;; http://www.zimmers.net/anonftp/pub/cbm/programming/serial-bus.pdf (page 11)
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iec_rx_byte:
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;; First, we wait for the talker to release the CLK line
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jsr iec_wait_for_clk_release
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;; We then release the DATA to signal we are ready
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;; We can use this routine, since we weren't pulling CLK anyway
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jsr iec_release_clk_data
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;; Wait for talker to pull CLK.
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;; If over 200 usec (205 cycles on NTSC machine) , then it is EOI.
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;; Loop iteraction takes 13 cycles, 17 full iterations are enough
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ldx #$11 ; 2 cycles
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iec_rx_clk_wait:
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lda CI2PRA ; 4 cycles
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rol ; 2 cycles, to put BIT_CI2PRA_CLK_IN as the last bit
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bpl iec_rx_not_eoi ; 2 cycles if not jumped
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dex ; 2 cycles
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bne iec_rx_clk_wait ; 3 cycles if jumped
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;; Timeout - wait for pulled CLK and pull data for 60 usec to confirm
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jsr iec_wait_for_clk_pull
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jsr iec_release_clk_pull_data
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jsr iec_wait60us
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jsr iec_release_clk_data
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;; Store EOI information in IOSTATUS - XXX this should be done by the caller!
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lda IOSTATUS
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ora #$40
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sta IOSTATUS
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sec
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rts
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; ;; First, we wait for the talker to release the CLK line.
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; ;; XXX jsr iec_wait_for_clock_release
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iec_rx_not_eoi:
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; ;; We then release the data line
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; ;; (We can use this routine, since we weren't holding CLK, anyway)
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; jsr iec_release_clk_and_data
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;; Latch input bits in on rising edge of CLK, eight times for eight bits.
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ldx #7
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; ;; Wait for talker to assert CLK.
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; ;; If >200usec, then it is EOI and we have to assert the
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; ;; DATA line for 60 usec to tell the TALKER that we have
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; ;; acknowledged the EOI.
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; ldx #20
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iec_rx_clk_wait:
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; ;; Loop takes 11 usec, so ~20 iterations for 200usec timeout
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; lda $dd00
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; rol
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; bpl not_eoi
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; dex
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; cpx #$21
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; bne not_rx_timeout
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; ;; Time out waiting for CLK to assert again.
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; ;; = error
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; sec
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; rts
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not_rx_timeout:
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; cpx #$00
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; bpl iec_rx_clk_wait
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; ;; Remember EOI condition
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; lda IOSTATUS
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; ora #$40
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; sta IOSTATUS
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; ;; EOI timeout: So pulse DATA line for 60 usec
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; jsr iec_assert_data
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; jsr iec_wait60us
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; jsr iec_release_clk_and_data
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; ;; And still wait for CLK to be asserted
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; ;; XXX - This will cause periodic EOI pulses if the sender takes too long.
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; ;; That is probably ok.
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; ldx #$7f
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; jmp iec_rx_clk_wait
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not_eoi:
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; ;; CLK is now low. Latch input bits in on rising edge
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; ;; of CLK, eight times for eight bits.
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; ldx #7
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; ;; Get empty byte to load into.
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; lda #$00
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; pha
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;; Get empty byte to load into.
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lda #$00
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pha
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iec_rx_bit_loop:
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; ;; Wait for CLK to release
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; ;; jsr iec_wait_for_clock_release
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; ;; (we do this implicitly below, with a tighter routine,
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; ;; so that we don't have timing problems, as the requirements
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; ;; are quite tight. Basically we need to read the clock and data
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; ;; bit from the same byte read.
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;; Wait for CLK to release
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jsr iec_wait_for_clk_release
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; ;; DATA now has the next bit, but inverted (well, except that it turns out not to be).
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; ;; DATA is in bit7, which is a bit annoying.
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; ;; But we can clock it out with a ROL instruction
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; ;; so that it is in C. We can then ROR it into the
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; ;; partial data byte.
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; ;; We use ROR so that we shift in from the top, so that
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; ;; the first bit we shift in ends up in bit 0 after all
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; ;; 8 bits have been read.
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; ;; ODD: For some reason we don't need to invert the
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; ;; received bits. This is weird, because we invert them
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; ;; on the way out, and everything in the protocol seems
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; ;; to indicate that we sould do so. But experimentation
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; ;; has confirmed the bits don't need inversion on reception.
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;; (we do this implicitly below, with a tighter routine,
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;; so that we don't have timing problems, as the requirements
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;; are quite tight. Basically we need to read the clock and data
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;; bit from the same byte read.
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; ;; Move data bit into C flag, and loop until bit 6 clears
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; ;; i.e., the clock has been released.
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;* LDA $DD00
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; ROL
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; bpl -
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;; DATA now has the next bit, but inverted (well, except that it turns out not to be).
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;; DATA is in bit 7, which is a bit annoying.
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;; But we can clock it out with a ROL instruction
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;; so that it is in C. We can then ROR it into the
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;; partial data byte.
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;; We use ROR so that we shift in from the top, so that
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;; the first bit we shift in ends up in bit 0 after all
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;; 8 bits have been read.
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;; ODD: For some reason we don't need to invert the
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;; received bits. This is weird, because we invert them
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;; on the way out, and everything in the protocol seems
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;; to indicate that we sould do so. But experimentation
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;; has confirmed the bits don't need inversion on reception.
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; ;; Pull it into the data byte
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;; pla
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; ROR
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; pha
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;; Move data bit into C flag, and loop until bit 6 clears
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;; i.e., the clock has been released.
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* lda CI2PRA
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rol
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bpl -
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; ;; Wait for CLK to re-assert
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; jsr iec_wait_for_clock_assert
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;; Pull it into the data byte
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pla
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ror
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pha
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; ;; More bits?
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; dex
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; bpl iec_rx_bit_loop
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;; Wait for CLK to be pulled again
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jsr iec_wait_for_clk_pull
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; ;; Then we must within 1000usec acknowledge the frame by
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; ;; asserting DATA. At this point, CLK is asserted by the
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; ;; talker and DATA by us, i.e., we are ready to receive
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; ;; the next byte. (p11).
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; jsr iec_assert_data
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;; More bits?
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dex
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bpl iec_rx_bit_loop
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; ;; Retreive the received byte
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; PLA
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;; Then we must within 1000 usec acknowledge the frame by
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;; pulling DATA. At this point, CLK is pulled by the
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;; talker and DATA by us, i.e., we are ready to receive
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;; the next byte. (p11).
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jsr iec_release_clk_pull_data
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; ;; Return no-error
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; CLC
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; RTS
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;; Retreive the received byte
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pla
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;; Return no-error
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clc
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rts
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@@ -1,39 +1,29 @@
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;; According to http://www.zimmers.net/anonftp/pub/cbm/programming/serial-bus.pdf
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;; pages 7--8.
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;; See also https://www.pagetable.com/?p=1135, https://github.com/mist64/cbmbus_doc
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iec_turnaround_to_listen:
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;; Assert data and release clock
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lda $dd00
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and #$ef ; release clock (bit 4)
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ora #$20 ; assert data (bit 5)
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sta $dd00
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;; Wait for clock line to be asserted by the drive
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* lda $dd00
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and #$40
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;; Pull DATA, release CLK and ATN (we are not sending commands)
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jsr iec_pull_data_release_atn_clock
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;; Wait for clock line to be pulled by the drive
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ldx #$FF ; XXX should we really use that high number?
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*
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lda CI2PRA
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rol ; to put BIT_CI2PRA_CLK_IN as the last (sign) bit
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bpl +
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dex
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bne -
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;; http://www.zimmers.net/anonftp/pub/cbm/programming/serial-bus.pdf
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;; page 8 tells us we should not do anything here after waiting for
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;; the clock line to assert.
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ldx #$ff
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* lda $dd00
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and #$40
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bne +
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dex
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bne -
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;; Timeout
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jsr printf
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.byte "DBG: TURNAROUND FAILED",$0d,$00
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sec
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rts
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;; jsr printf
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;; .byte "TURNAROUND FAILED - FILE NOT FOUND?",$0d,$00
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;; ;; Timeout = file not found error
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;; ;; (https://www.pagetable.com/?p=1023)
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lda #4
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sec
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rts
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*
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;; ATN turn around successful
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;; CLK is pulled by the device, OK
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*
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clc
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rts
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@@ -35,7 +35,7 @@ iec_tx_command:
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;; Common part of iec_txbyte and iec_tx_common - waits for devices
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;; and transmits a byte
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pla
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jsr iec_tx_common
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@@ -6,11 +6,12 @@ iec_tx_common:
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;; Store the bye to send on a stack
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pha
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;; Wait till all receivers are ready, they should all release DATA
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jsr iec_wait_for_data_release
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;; Pull CLK back to indicate that DATA is not valid, keep it for 60us
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;; We can use this routine as we don't hold DATA anyway (and its state doesn't even matter)
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;; Don't wait too long, as 200us or more is considered EOI
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jsr iec_pull_clk_release_data
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@@ -42,11 +43,14 @@ iec_tx_common_bit_is_sent:
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pla
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dex
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bpl iec_tx_common_nextbit
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;; Whole byte send, make sure ATN is released
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jsr iec_release_atn_clk_data
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;; XXX the flow below is REALLY dangerous, as if there are multiple devices,
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;; one can signal that it's busy much earlier (more than 100ms) than the other.
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;; Can we do something about it?
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;; All done - give devices time to tell if they are busy by pulling DATA
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;; They should do it within 1ms
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ldx #$FF
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@@ -62,7 +66,9 @@ iec_tx_common_bit_is_sent:
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jsr iec_wait100us
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iec_tx_common_done:
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;; Byte sent, return
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clc
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rts
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iec_tx_common_nextbit:
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@@ -1,9 +1,10 @@
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iec_tx_eoi:
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;; Wait at least 200us
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;; Wait at least 256 usec
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jsr iec_wait100us
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jsr iec_wait100us
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jsr iec_wait60us
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;; Restore the bus to idle state
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jsr iec_set_idle
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@@ -4,9 +4,9 @@ iec_wait100us:
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;; Wait 100usec
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;; PAL:
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;; - CPU frequency 0.985248 MHz, we need to waste at least 102 cycles
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;; - CPU frequency 0.985248 MHz, we need to waste at least 99 cycles
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;; NTSC:
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;; - CPU frequency 1.022727 MHZ, we need to waste at least 98 cycles
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;; - CPU frequency 1.022727 MHZ, we need to waste at least 103 cycles
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;; Waste cycles by reading some unimportant memory location
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;; (in a loop) in order not to clutter VICE debug logs
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@@ -4,9 +4,9 @@ iec_wait20us:
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;; Wait 20usec
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;; PAL:
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;; - CPU frequency 0.985248 MHz, we need to waste at least 21 cycles
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;; - CPU frequency 0.985248 MHz, we need to waste at least 20 cycles
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;; NTSC:
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;; - CPU frequency 1.022727 MHZ, we need to waste at least 20 cycles
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;; - CPU frequency 1.022727 MHZ, we need to waste at least 21 cycles
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;; Waste cycles by reading some unimportant memory location
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;; in order not to clutter VICE debug logs
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@@ -4,9 +4,9 @@ iec_wait60us:
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;; Wait 60usec
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;; PAL:
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;; - CPU frequency 0.985248 MHz, we need to waste at least 61 cycles
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;; - CPU frequency 0.985248 MHz, we need to waste at least 60 cycles
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;; NTSC:
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;; - CPU frequency 1.022727 MHZ, we need to waste at least 59 cycles
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;; - CPU frequency 1.022727 MHZ, we need to waste at least 62 cycles
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;; Waste cycles in a loop
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@@ -0,0 +1,6 @@
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iec_wait_for_clk_pull:
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lda CI2PRA
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rol ; to put BIT_CI2PRA_CLK_IN as the last (sign) bit
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bmi iec_wait_for_clk_pull
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rts
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@@ -0,0 +1,6 @@
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iec_wait_for_clk_release:
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lda CI2PRA
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and #BIT_CI2PRA_CLK_IN
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beq iec_wait_for_clk_release
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rts
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+17
-11
@@ -15,9 +15,6 @@ open:
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bcs +
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bmi open_has_space
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*
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jsr printf
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.byte "FULL", $0D, 0
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;; Table is full - according to https://codebase64.org/doku.php?id=base:kernalreference
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;; C flag set means error occured
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sec
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@@ -74,11 +71,9 @@ open_rs232:
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open_iec:
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;; XXX add FILENAM support, test it
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;; Part implemented according to https://www.pagetable.com/?p=1031, https://github.com/mist64/cbmbus_doc
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;; Sequence is:
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;; 1. Call current device to attention as LISTENER = $20 + device
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;; 2.
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;; XXX for now for channel 15 only!
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;; Disable IRQs, since timing matters!
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sei
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@@ -86,14 +81,25 @@ open_iec:
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;; Begin sending under attention
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;; XXX jsr iec_assert_atn
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;; CLK is now asserted, and we are ready to transmit a byte
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;; Request device to talk
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lda current_device_number
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jsr listen
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bcs open_iec_error
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jsr talk
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bcs open_iec_error ; XXX what about the accumulator?
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jsr printf
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.byte "DBG: OPEN 1", $0D, 0
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;; Send secondary address
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lda current_secondary_address
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jsr tksa
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bcs open_iec_error ; XXX what about the accumulator?
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jsr printf
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.byte "DBG: OPEN 2", $0D, 0
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;; Indicate success
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lda #$00
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clc
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clc
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open_iec_error:
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;; Re-enable interrupts and return
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@@ -1,3 +1,12 @@
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; Function defined on pp272-273 of C64 Programmers Reference Guide
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tksa:
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;; This routine is documented in 'C64 Programmer's Reference Guide', page 302 and
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;; https://www.pagetable.com/?p=1031, , https://github.com/mist64/cbmbus_doc
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ora #$F0
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jsr iec_tx_command
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bcs tksa_error
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jmp iec_turnaround_to_listen
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tksa_error:
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rts
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