more work towards IEC bus. Also don't corrupt $DD00 VIC-II bank bits in the process.

This commit is contained in:
Paul Gardner-Stephen committed 2019-05-01 21:47:00 +09:30
1 parent 16dcfbe22b
commit 687ed9c56a
7 files changed
+54 -36

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+1 -1
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@@ -1,6 +1,6 @@
iec_assert_clk_and_data:
lda $dd00
and #$08
and #$0b
ora #$30
sta $dd00
rts
+1 -1
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@@ -1,6 +1,6 @@
iec_assert_clk_release_data:
lda $dd00
and #$08
and #$0b
ora #$10
sta $dd00
rts
+1 -1
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@@ -1,5 +1,5 @@
iec_release_clk:
lda $dd00
and #$18
and #$1b
sta $dd00
rts
+1 -1
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@@ -1,6 +1,6 @@
iec_release_clk_and_data:
lda $DD00
and #$08
and #$0b
sta $DD00
rts
+36 -1
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@@ -1,8 +1,44 @@
iec_tx_byte:
pha
jsr iec_assert_clk_release_data
;; Give devices time to respond
jsr wait1ms
;; Did a device respond? (DATA will be pulled if so)
lda $DD00
bmi +
;; No devices present, so we can immediately return with device not found
pla
jmp kernalerror_DEVICE_NOT_FOUND
*
;; Release CLK and wait for DATA to release.
jsr iec_release_clk_and_data
;; Wait for DATA to be released
;; Listener is allowed to hold DATA for as long as they want.
;; i.e., this is the part of the protocol where the listener indicates
;; that they are busy doing something, like processing the previous
;; character.
jsr iec_wait_for_data_release
;; We then wait for 60 usec (less than 200usec so we don't
;; signal EOI), before asserting CLK again.
jsr iec_wait60us
;; Re-assert CLK line
jsr iec_assert_clk_release_data
;; Do the actual transmission of 8 bits of data
ldx #8
pla
iec_tx_byte_nextbit:
;; Is next bit 0 or 1?
lsr
@@ -40,7 +76,6 @@ iec_tx_byte_l1:
bne -
;; Timeout - DEVICE NOT PRESENT
cli
jmp kernalerror_DEVICE_NOT_FOUND
*
;; All done.
+12 -31
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@@ -11,38 +11,19 @@ open:
;; Begin sending under attention
jsr iec_assert_atn
jsr iec_assert_clk_release_data
;; Give devices time to respond
jsr wait1ms
;; Did a device respond? (DATA will be pulled if so)
lda $DD00
bmi +
;; No devices present, so we can immediately return with device not found
cli
jmp kernalerror_DEVICE_NOT_FOUND
*
;; Release CLK and wait for DATA to release.
jsr iec_release_clk_and_data
;; Wait for DATA to be released
;; Listener is allowed to hold DATA for as long as they want.
;; i.e., this is the part of the protocol where the listener indicates
;; that they are busy doing something, like processing the previous
;; character.
jsr iec_wait_for_data_release
;; We then wait for 60 usec (less than 200usec so we don't
;; signal EOI), before asserting CLK again.
jsr iec_wait60us
;; Re-assert CLK line
jsr iec_assert_clk_release_data
;; CLK is now asserted, and we are ready to transmit a byte
lda #$28
jsr iec_tx_byte
bcs open_error
;; Indicate success
lda #$00
clc
open_error:
;; Re-enable interrupts and return
;; (iec_tx_byte will have set/cleared C flag and put result code
;; in A if it was an error).
cli
rts
+2
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@@ -29,6 +29,8 @@ reset_entry:
; What do we do when finished? A C64 jumps into the BASIC ROM
cli ; Allow interrupts to happen
jsr open
; c64 prg p269
jmp ($a000)