more work towards IEC bus. Also don't corrupt $DD00 VIC-II bank bits in the process.
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@@ -1,6 +1,6 @@
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iec_assert_clk_and_data:
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lda $dd00
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and #$08
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and #$0b
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ora #$30
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sta $dd00
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rts
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@@ -1,6 +1,6 @@
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iec_assert_clk_release_data:
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lda $dd00
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and #$08
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and #$0b
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ora #$10
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sta $dd00
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rts
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@@ -1,5 +1,5 @@
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iec_release_clk:
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lda $dd00
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and #$18
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and #$1b
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sta $dd00
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rts
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@@ -1,6 +1,6 @@
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iec_release_clk_and_data:
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lda $DD00
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and #$08
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and #$0b
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sta $DD00
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rts
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@@ -1,8 +1,44 @@
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iec_tx_byte:
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pha
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jsr iec_assert_clk_release_data
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;; Give devices time to respond
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jsr wait1ms
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;; Did a device respond? (DATA will be pulled if so)
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lda $DD00
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bmi +
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;; No devices present, so we can immediately return with device not found
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pla
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jmp kernalerror_DEVICE_NOT_FOUND
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*
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;; Release CLK and wait for DATA to release.
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jsr iec_release_clk_and_data
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;; Wait for DATA to be released
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;; Listener is allowed to hold DATA for as long as they want.
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;; i.e., this is the part of the protocol where the listener indicates
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;; that they are busy doing something, like processing the previous
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;; character.
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jsr iec_wait_for_data_release
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;; We then wait for 60 usec (less than 200usec so we don't
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;; signal EOI), before asserting CLK again.
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jsr iec_wait60us
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;; Re-assert CLK line
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jsr iec_assert_clk_release_data
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;; Do the actual transmission of 8 bits of data
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ldx #8
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pla
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iec_tx_byte_nextbit:
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;; Is next bit 0 or 1?
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lsr
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@@ -40,7 +76,6 @@ iec_tx_byte_l1:
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bne -
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;; Timeout - DEVICE NOT PRESENT
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cli
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jmp kernalerror_DEVICE_NOT_FOUND
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*
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;; All done.
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+12
-31
@@ -11,38 +11,19 @@ open:
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;; Begin sending under attention
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jsr iec_assert_atn
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jsr iec_assert_clk_release_data
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;; Give devices time to respond
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jsr wait1ms
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;; Did a device respond? (DATA will be pulled if so)
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lda $DD00
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bmi +
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;; No devices present, so we can immediately return with device not found
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cli
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jmp kernalerror_DEVICE_NOT_FOUND
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*
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;; Release CLK and wait for DATA to release.
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jsr iec_release_clk_and_data
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;; Wait for DATA to be released
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;; Listener is allowed to hold DATA for as long as they want.
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;; i.e., this is the part of the protocol where the listener indicates
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;; that they are busy doing something, like processing the previous
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;; character.
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jsr iec_wait_for_data_release
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;; We then wait for 60 usec (less than 200usec so we don't
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;; signal EOI), before asserting CLK again.
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jsr iec_wait60us
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;; Re-assert CLK line
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jsr iec_assert_clk_release_data
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;; CLK is now asserted, and we are ready to transmit a byte
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lda #$28
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jsr iec_tx_byte
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bcs open_error
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;; Indicate success
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lda #$00
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clc
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open_error:
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;; Re-enable interrupts and return
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;; (iec_tx_byte will have set/cleared C flag and put result code
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;; in A if it was an error).
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cli
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rts
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@@ -29,6 +29,8 @@ reset_entry:
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; What do we do when finished? A C64 jumps into the BASIC ROM
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cli ; Allow interrupts to happen
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jsr open
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; c64 prg p269
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jmp ($a000)
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