JiffyDOS byte tx fixes
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17de034a1a
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6bfaadff78
1 file changed
+9
-8
@@ -23,7 +23,7 @@ iec_tx_byte_jiffydos:
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// Preserve .X (.Y is not used by the routine)
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phx_trash_a
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// If EOI requested (carryy flag set), mark this in IECPROTO as 0
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// If EOI requested (carry flag set), mark this in IECPROTO as 0
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bcc !+
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dec IECPROTO // turns 1 into 0
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!:
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@@ -47,6 +47,9 @@ iec_tx_byte_jiffydos:
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and #$F0
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pha
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// Prepare value for device notification
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ldx C3PO
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// Wait till receiver is ready
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jsr iec_wait_for_data_release
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@@ -56,17 +59,16 @@ __jd_check1:
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jsr jiffydos_wait_line
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// Notify device that we are going to send byte by releasing everything
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// Cycles: 3 + 4 = 7
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lda C3PO
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sta CIA2_PRA
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stx CIA2_PRA // cycles: 4
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// Send high nibble; cycles: 4 + 3 + 4 + 2 + 2 + 2 + 4 = 21
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// Send high nibble; cycles: 4 + 3 + 4 + 2 + 2 + 2 + 3 + 4 = 24
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pla // retrieve high nibble from stack
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ora C3PO // restore VIC-II and RS-232 bits
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sta CIA2_PRA // bits 4 and 5 on CLK/DATA
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ror // move bits 6 and 7 to positions 4 and 5
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ror
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and #%00110000 // clear everything but CLK/DATA
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ora C3PO
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sta CIA2_PRA // bits 6 and 7 on CLK/DATA
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// Send low nibble; cycles: 4 + 3 + 4 + 2 + 2 + 2 + 4 = 21
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@@ -78,7 +80,7 @@ __jd_check1:
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and #%00110000 // clear everything but CLK/DATA
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sta CIA2_PRA
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// Signal EOI if needed XXX calculate cycles for quickly pulling CLK
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// Signal EOI if needed; cycles till no EOI: 3 + 3 + 2 + 2 + 4 = 14
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lda C3PO
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ldx IECPROTO
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beq iec_tx_byte_jiffydos_wait_eoi
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@@ -176,8 +178,7 @@ jiffydos_wait_line:
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// To give the transfer routine as much time as possible,
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// wait till a badline
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// XXX this is probably overkill, most likely it is enough to avoid 2 (3?) lines
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// before badline - to be adjusted in the future
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// XXX probably overkill, most likely it is enough to avoid 2 lines before badline
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!:
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sec
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lda VIC_SCROLY
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