chris/open-roms
1
0 Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

more Z80 work

Browse Source
This commit is contained in:
FeralChild64 authored and FeralChild64 committed 2021-01-26 00:03:07 +01:00
1 parent 24b3f9ebdb
commit 76ed769d7b
7 files changed
+608 -210
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

src/zvm_m65/,aliases_zvm.s
+62 -61
View File
@@ -1,72 +1,73 @@
!addr REG_AF = $02 ; 16-bit combined register
!addr REG_F = REG_AF+0 ; 8-bit flag register
!addr REG_A = REG_AF+1 ; 8-bit accumulator
!addr REG_BC = $04
!addr REG_C = REG_BC+0
!addr REG_B = REG_BC+1
!addr REG_DE = $06
!addr REG_E = REG_DE+0
!addr REG_D = REG_DE+1
!addr REG_HL = $08
!addr REG_L = REG_HL+0
!addr REG_H = REG_HL+1
!addr REG_AF = $02 ; 16-bit combined register
!addr REG_F = REG_AF+0 ; 8-bit flag register
!addr REG_A = REG_AF+1 ; 8-bit accumulator
!addr REG_BC = $04
!addr REG_C = REG_BC+0
!addr REG_B = REG_BC+1
!addr REG_DE = $06
!addr REG_E = REG_DE+0
!addr REG_D = REG_DE+1
!addr REG_HL = $08
!addr REG_L = REG_HL+0
!addr REG_H = REG_HL+1
!addr REG_F_SH = $0A ; shadow registers
!addr REG_A_SH = $0B
!addr REG_C_SH = $0C
!addr REG_B_SH = $0D
!addr REG_E_SH = $0E
!addr REG_D_SH = $0F
!addr REG_L_SH = $10
!addr REG_H_SH = $11
!addr REG_F_SH = $0A ; shadow registers
!addr REG_A_SH = $0B
!addr REG_C_SH = $0C
!addr REG_B_SH = $0D
!addr REG_E_SH = $0E
!addr REG_D_SH = $0F
!addr REG_L_SH = $10
!addr REG_H_SH = $11
!addr REG_IX = $12 ; 16-bit index register
!addr REG_IXL = $12
!addr REG_IXH = $13
!addr REG_IY = $14 ; 16-bit index register
!addr REG_IYL = $14
!addr REG_IYH = $15
!addr REG_SP = $16 ; 16-bit stack pointer
!addr REG_PC = $18 ; 16-bit program counter
!addr REG_IX = $12 ; 16-bit index register
!addr REG_IXL = $12
!addr REG_IXH = $13
!addr REG_IY = $14 ; 16-bit index register
!addr REG_IYL = $14
!addr REG_IYH = $15
!addr REG_SP = $16 ; 16-bit stack pointer
!addr REG_PC = $18 ; 16-bit program counter
!addr REG_I = $1A ; 8-bit interrupt vector base
!addr REG_R06 = $1B ; refresh counter, bits 0-6 (bit 7 is garbage)
!addr REG_R7 = $1C ; refresh counter, bit 7 (bits 0-6 are garbage)
!addr REG_I = $1A ; 8-bit interrupt vector base
!addr REG_R06 = $1B ; refresh counter, bits 0-6 (bit 7 is garbage)
!addr REG_R7 = $1C ; refresh counter, bit 7 (bits 0-6 are garbage)
!addr PTR_IXY_d = $1D ; 16-bit calculated address IX+d / IY+d XXX - important!!!
!addr PTR_DATA = $1F ; data source address XXX - important!!!
!addr PTR_IXY_d = $1D ; 16-bit calculated address IX+d / IY+d XXX - important!!!
!addr PTR_DATA = $1F ; data source address XXX - important!!!
!addr REG_IFF1 = $23 ; interrupt flip-flop flag 1
!addr REG_IFF2 = $24 ; interrupt flip-flop flag 2
!addr REG_TMP1 = $25 ; emulation-specific temporary storage
!addr REG_TMP2 = $26
!addr ADDR_IO = $27 ; 16-bit address for fetching/storing the IO
!addr REG_IFF1 = $23 ; interrupt flip-flop flag 1
!addr REG_IFF2 = $24 ; interrupt flip-flop flag 2
!addr REG_TMP1 = $25 ; emulation-specific temporary storage
!addr REG_TMP2 = $26
!addr ADDR_IO = $27 ; 16-bit address for fetching/storing the IO
!addr VEC_MOVE_fetch = $30 ; vector to byte fetch routine, for BIOS routine MOVE
!addr VEC_MOVE_store = $32 ; vector to byte store routine, for BIOS routine MOVE
!addr VEC_DISKIO_store = $34 ; vector to byte store routine, for BIOS disk I/O operations
!addr VEC_fetch_value = $60
!addr VEC_fetch_stack = $62
!addr VEC_store_stack = $64
!addr VEC_fetch_via_BC = $66 ; XXX add routines
!addr VEC_store_via_BC = $68 ; XXX add routines
!addr VEC_fetch_via_DE = $6A ; XXX add routines
!addr VEC_store_via_DE = $6C ; XXX add routines
!addr VEC_fetch_via_HL = $6E
!addr VEC_store_via_HL = $70
!addr VEC_fetch_via_IX_d = $72
!addr VEC_fetch_via_IY_d = $74
!addr VEC_store_via_IX_d = $76
!addr VEC_store_via_IY_d = $78
!addr VEC_fetch_via_nn = $7A
!addr VEC_store_via_nn = $7C
!addr VEC_MOVE_fetch = $30 ; vector to byte fetch routine, for BIOS routine MOVE
!addr VEC_MOVE_store = $32 ; vector to byte store routine, for BIOS routine MOVE
!addr VEC_DISKIO_store = $34 ; vector to byte store routine, for BIOS disk I/O operations
!addr VEC_fetch_value = $50
!addr VEC_fetch_stack = $52
!addr VEC_store_stack = $54
!addr VEC_fetch_via_BC = $56 ; XXX add routines
!addr VEC_store_via_BC = $58 ; XXX add routines
!addr VEC_fetch_via_DE = $5A ; XXX add routines
!addr VEC_store_via_DE = $5C ; XXX add routines
!addr VEC_fetch_via_HL = $5E
!addr VEC_store_via_HL = $60
!addr VEC_fetch_via_IX_d = $62
!addr VEC_fetch_via_IY_d = $64
!addr VEC_store_via_IX_d = $66
!addr VEC_store_via_IY_d = $68
!addr VEC_fetch_via_nn = $6A
!addr VEC_store_via_nn = $6C
!addr VEC_fetch_via_plus1 = $6E ; XXX add routines
!addr VEC_store_via_plus1 = $70 ; XXX add routines XXX jump to next directly?
!addr VEC_xchng_stack_lo = $72 ; XXX add routines
!addr VEC_xchng_stack_hi = $74 ; XXX add routines
; Masks for Z80 flag (F) register
src/zvm_m65/z80_instr_bit_sizeopt.s
+392
View File
@@ -3,3 +3,395 @@
; Z80 bit set/reset/test instructions - these illegals are size optimized
;
!macro Z80_RES0_VIA_IXY_d_REGn .REGn {
lda [PTR_IXY_d],z
and #%11111110
sta .REGn
bra Z80_common_res_0123
}
!macro Z80_RES1_VIA_IXY_d_REGn .REGn {
lda [PTR_IXY_d],z
and #%11111101
sta .REGn
bra Z80_common_res_0123
}
!macro Z80_RES2_VIA_IXY_d_REGn .REGn {
lda [PTR_IXY_d],z
and #%11111011
sta .REGn
bra Z80_common_res_0123
}
!macro Z80_RES3_VIA_IXY_d_REGn .REGn {
lda [PTR_IXY_d],z
and #%11110111
sta .REGn
bra Z80_common_res_0123
}
!macro Z80_RES4_VIA_IXY_d_REGn .REGn {
lda [PTR_IXY_d],z
and #%11101111
sta .REGn
bra Z80_common_res_4567
}
!macro Z80_RES5_VIA_IXY_d_REGn .REGn {
lda [PTR_IXY_d],z
and #%11011111
sta .REGn
bra Z80_common_res_4567
}
!macro Z80_RES6_VIA_IXY_d_REGn .REGn {
lda [PTR_IXY_d],z
and #%10111111
sta .REGn
bra Z80_common_res_4567
}
!macro Z80_RES7_VIA_IXY_d_REGn .REGn {
lda [PTR_IXY_d],z
and #%01111111
sta .REGn
bra Z80_common_res_4567
}
Z80_illeg_xDCB_80: +Z80_RES0_VIA_IXY_d_REGn REG_B ; RES 0,(IXY+d),B
Z80_illeg_xDCB_81: +Z80_RES0_VIA_IXY_d_REGn REG_C ; RES 0,(IXY+d),C
Z80_illeg_xDCB_82: +Z80_RES0_VIA_IXY_d_REGn REG_D ; RES 0,(IXY+d),D
Z80_illeg_xDCB_83: +Z80_RES0_VIA_IXY_d_REGn REG_E ; RES 0,(IXY+d),E
Z80_illeg_xDCB_84: +Z80_RES0_VIA_IXY_d_REGn REG_H ; RES 0,(IXY+d),H
Z80_illeg_xDCB_85: +Z80_RES0_VIA_IXY_d_REGn REG_L ; RES 0,(IXY+d),L
Z80_illeg_xDCB_88: +Z80_RES1_VIA_IXY_d_REGn REG_B ; RES 1,(IXY+d),B
Z80_illeg_xDCB_89: +Z80_RES1_VIA_IXY_d_REGn REG_C ; RES 1,(IXY+d),C
Z80_illeg_xDCB_8A: +Z80_RES1_VIA_IXY_d_REGn REG_D ; RES 1,(IXY+d),D
Z80_illeg_xDCB_8B: +Z80_RES1_VIA_IXY_d_REGn REG_E ; RES 1,(IXY+d),E
Z80_illeg_xDCB_8C: +Z80_RES1_VIA_IXY_d_REGn REG_H ; RES 1,(IXY+d),H
Z80_illeg_xDCB_8D: +Z80_RES1_VIA_IXY_d_REGn REG_L ; RES 1,(IXY+d),L
lda [PTR_IXY_d],z
and #%11111101
sta REG_L
; FALLTROUGH
Z80_common_res_0123:
sta [PTR_IXY_d],z
jmp ZVM_next
Z80_illeg_xDCB_90: +Z80_RES2_VIA_IXY_d_REGn REG_B ; RES 2,(IXY+d),B
Z80_illeg_xDCB_91: +Z80_RES2_VIA_IXY_d_REGn REG_C ; RES 2,(IXY+d),C
Z80_illeg_xDCB_92: +Z80_RES2_VIA_IXY_d_REGn REG_D ; RES 2,(IXY+d),D
Z80_illeg_xDCB_93: +Z80_RES2_VIA_IXY_d_REGn REG_E ; RES 2,(IXY+d),E
Z80_illeg_xDCB_94: +Z80_RES2_VIA_IXY_d_REGn REG_H ; RES 2,(IXY+d),H
Z80_illeg_xDCB_95: +Z80_RES2_VIA_IXY_d_REGn REG_L ; RES 2,(IXY+d),L
Z80_illeg_xDCB_98: +Z80_RES3_VIA_IXY_d_REGn REG_B ; RES 3,(IXY+d),B
Z80_illeg_xDCB_99: +Z80_RES3_VIA_IXY_d_REGn REG_C ; RES 3,(IXY+d),C
Z80_illeg_xDCB_9A: +Z80_RES3_VIA_IXY_d_REGn REG_D ; RES 3,(IXY+d),D
Z80_illeg_xDCB_9B: +Z80_RES3_VIA_IXY_d_REGn REG_E ; RES 3,(IXY+d),E
Z80_illeg_xDCB_9C: +Z80_RES3_VIA_IXY_d_REGn REG_H ; RES 3,(IXY+d),H
Z80_illeg_xDCB_9D: +Z80_RES3_VIA_IXY_d_REGn REG_L ; RES 3,(IXY+d),L
Z80_illeg_xDCB_A0: +Z80_RES4_VIA_IXY_d_REGn REG_B ; RES 4,(IXY+d),B
Z80_illeg_xDCB_A1: +Z80_RES4_VIA_IXY_d_REGn REG_C ; RES 4,(IXY+d),C
Z80_illeg_xDCB_A2: +Z80_RES4_VIA_IXY_d_REGn REG_D ; RES 4,(IXY+d),D
Z80_illeg_xDCB_A3: +Z80_RES4_VIA_IXY_d_REGn REG_E ; RES 4,(IXY+d),E
Z80_illeg_xDCB_A4: +Z80_RES4_VIA_IXY_d_REGn REG_H ; RES 4,(IXY+d),H
Z80_illeg_xDCB_A5: +Z80_RES4_VIA_IXY_d_REGn REG_L ; RES 4,(IXY+d),L
Z80_illeg_xDCB_A8: +Z80_RES5_VIA_IXY_d_REGn REG_B ; RES 5,(IXY+d),B
Z80_illeg_xDCB_A9: +Z80_RES5_VIA_IXY_d_REGn REG_C ; RES 5,(IXY+d),C
Z80_illeg_xDCB_AA: +Z80_RES5_VIA_IXY_d_REGn REG_D ; RES 5,(IXY+d),D
Z80_illeg_xDCB_AB: +Z80_RES5_VIA_IXY_d_REGn REG_E ; RES 5,(IXY+d),E
Z80_illeg_xDCB_AC: +Z80_RES5_VIA_IXY_d_REGn REG_H ; RES 5,(IXY+d),H
Z80_illeg_xDCB_AD: +Z80_RES5_VIA_IXY_d_REGn REG_L ; RES 5,(IXY+d),L
lda [PTR_IXY_d],z
and #%11011111
sta REG_L
; FALLTROUGH
Z80_common_res_4567:
sta [PTR_IXY_d],z
jmp ZVM_next
Z80_illeg_xDCB_B0: +Z80_RES6_VIA_IXY_d_REGn REG_B ; RES 6,(IXY+d),B
Z80_illeg_xDCB_B1: +Z80_RES6_VIA_IXY_d_REGn REG_C ; RES 6,(IXY+d),C
Z80_illeg_xDCB_B2: +Z80_RES6_VIA_IXY_d_REGn REG_D ; RES 6,(IXY+d),D
Z80_illeg_xDCB_B3: +Z80_RES6_VIA_IXY_d_REGn REG_E ; RES 6,(IXY+d),E
Z80_illeg_xDCB_B4: +Z80_RES6_VIA_IXY_d_REGn REG_H ; RES 6,(IXY+d),H
Z80_illeg_xDCB_B5: +Z80_RES6_VIA_IXY_d_REGn REG_L ; RES 6,(IXY+d),L
Z80_illeg_xDCB_B8: +Z80_RES7_VIA_IXY_d_REGn REG_B ; RES 7,(IXY+d),B
Z80_illeg_xDCB_B9: +Z80_RES7_VIA_IXY_d_REGn REG_C ; RES 7,(IXY+d),C
Z80_illeg_xDCB_BA: +Z80_RES7_VIA_IXY_d_REGn REG_D ; RES 7,(IXY+d),D
Z80_illeg_xDCB_BB: +Z80_RES7_VIA_IXY_d_REGn REG_E ; RES 7,(IXY+d),E
Z80_illeg_xDCB_BC: +Z80_RES7_VIA_IXY_d_REGn REG_H ; RES 7,(IXY+d),H
Z80_illeg_xDCB_BD: +Z80_RES7_VIA_IXY_d_REGn REG_L ; RES 7,(IXY+d),L
!macro Z80_SET0_VIA_IXY_d_REGn .REGn {
lda [PTR_IXY_d],z
ora #%00000001
sta .REGn
bra Z80_common_set_0123
}
!macro Z80_SET1_VIA_IXY_d_REGn .REGn {
lda [PTR_IXY_d],z
ora #%00000010
sta .REGn
bra Z80_common_set_0123
}
!macro Z80_SET2_VIA_IXY_d_REGn .REGn {
lda [PTR_IXY_d],z
ora #%00000100
sta .REGn
bra Z80_common_set_0123
}
!macro Z80_SET3_VIA_IXY_d_REGn .REGn {
lda [PTR_IXY_d],z
ora #%00001000
sta .REGn
bra Z80_common_set_0123
}
!macro Z80_SET4_VIA_IXY_d_REGn .REGn {
lda [PTR_IXY_d],z
ora #%00010000
sta .REGn
bra Z80_common_set_4567
}
!macro Z80_SET5_VIA_IXY_d_REGn .REGn {
lda [PTR_IXY_d],z
ora #%00100000
sta .REGn
bra Z80_common_set_4567
}
!macro Z80_SET6_VIA_IXY_d_REGn .REGn {
lda [PTR_IXY_d],z
ora #%01000000
sta .REGn
bra Z80_common_set_4567
}
!macro Z80_SET7_VIA_IXY_d_REGn .REGn {
lda [PTR_IXY_d],z
ora #%10000000
sta .REGn
bra Z80_common_set_4567
}
Z80_illeg_xDCB_C0: +Z80_SET0_VIA_IXY_d_REGn REG_B ; SET 0,(IXY+d),B
Z80_illeg_xDCB_C1: +Z80_SET0_VIA_IXY_d_REGn REG_C ; SET 0,(IXY+d),C
Z80_illeg_xDCB_C2: +Z80_SET0_VIA_IXY_d_REGn REG_D ; SET 0,(IXY+d),D
Z80_illeg_xDCB_C3: +Z80_SET0_VIA_IXY_d_REGn REG_E ; SET 0,(IXY+d),E
Z80_illeg_xDCB_C4: +Z80_SET0_VIA_IXY_d_REGn REG_H ; SET 0,(IXY+d),H
Z80_illeg_xDCB_C5: +Z80_SET0_VIA_IXY_d_REGn REG_L ; SET 0,(IXY+d),L
Z80_illeg_xDCB_C8: +Z80_SET1_VIA_IXY_d_REGn REG_B ; SET 1,(IXY+d),B
Z80_illeg_xDCB_C9: +Z80_SET1_VIA_IXY_d_REGn REG_C ; SET 1,(IXY+d),C
Z80_illeg_xDCB_CA: +Z80_SET1_VIA_IXY_d_REGn REG_D ; SET 1,(IXY+d),D
Z80_illeg_xDCB_CB: +Z80_SET1_VIA_IXY_d_REGn REG_E ; SET 1,(IXY+d),E
Z80_illeg_xDCB_CC: +Z80_SET1_VIA_IXY_d_REGn REG_H ; SET 1,(IXY+d),H
Z80_illeg_xDCB_CD: ; SET 1,(IXY+d),L
lda [PTR_IXY_d],z
ora #%00000010
sta REG_L
; FALLTROUGH
Z80_common_set_0123:
sta [PTR_IXY_d],z
jmp ZVM_next
Z80_illeg_xDCB_D0: +Z80_SET2_VIA_IXY_d_REGn REG_B ; SET 2,(IXY+d),B
Z80_illeg_xDCB_D1: +Z80_SET2_VIA_IXY_d_REGn REG_C ; SET 2,(IXY+d),C
Z80_illeg_xDCB_D2: +Z80_SET2_VIA_IXY_d_REGn REG_D ; SET 2,(IXY+d),D
Z80_illeg_xDCB_D3: +Z80_SET2_VIA_IXY_d_REGn REG_E ; SET 2,(IXY+d),E
Z80_illeg_xDCB_D4: +Z80_SET2_VIA_IXY_d_REGn REG_H ; SET 2,(IXY+d),H
Z80_illeg_xDCB_D5: +Z80_SET2_VIA_IXY_d_REGn REG_L ; SET 2,(IXY+d),L
Z80_illeg_xDCB_D8: +Z80_SET3_VIA_IXY_d_REGn REG_B ; SET 3,(IXY+d),B
Z80_illeg_xDCB_D9: +Z80_SET3_VIA_IXY_d_REGn REG_C ; SET 3,(IXY+d),C
Z80_illeg_xDCB_DA: +Z80_SET3_VIA_IXY_d_REGn REG_D ; SET 3,(IXY+d),D
Z80_illeg_xDCB_DB: +Z80_SET3_VIA_IXY_d_REGn REG_E ; SET 3,(IXY+d),E
Z80_illeg_xDCB_DC: +Z80_SET3_VIA_IXY_d_REGn REG_H ; SET 3,(IXY+d),H
Z80_illeg_xDCB_DD: +Z80_SET3_VIA_IXY_d_REGn REG_L ; SET 3,(IXY+d),L
Z80_illeg_xDCB_E0: +Z80_SET4_VIA_IXY_d_REGn REG_B ; SET 4,(IXY+d),B
Z80_illeg_xDCB_E1: +Z80_SET4_VIA_IXY_d_REGn REG_C ; SET 4,(IXY+d),C
Z80_illeg_xDCB_E2: +Z80_SET4_VIA_IXY_d_REGn REG_D ; SET 4,(IXY+d),D
Z80_illeg_xDCB_E3: +Z80_SET4_VIA_IXY_d_REGn REG_E ; SET 4,(IXY+d),E
Z80_illeg_xDCB_E4: +Z80_SET4_VIA_IXY_d_REGn REG_H ; SET 4,(IXY+d),H
Z80_illeg_xDCB_E5: +Z80_SET4_VIA_IXY_d_REGn REG_L ; SET 4,(IXY+d),L
Z80_illeg_xDCB_E8: +Z80_SET5_VIA_IXY_d_REGn REG_B ; SET 5,(IXY+d),B
Z80_illeg_xDCB_E9: +Z80_SET5_VIA_IXY_d_REGn REG_C ; SET 5,(IXY+d),C
Z80_illeg_xDCB_EA: +Z80_SET5_VIA_IXY_d_REGn REG_D ; SET 5,(IXY+d),D
Z80_illeg_xDCB_EB: +Z80_SET5_VIA_IXY_d_REGn REG_E ; SET 5,(IXY+d),E
Z80_illeg_xDCB_EC: +Z80_SET5_VIA_IXY_d_REGn REG_H ; SET 5,(IXY+d),H
Z80_illeg_xDCB_ED: ; SET 5,(IXY+d),L
lda [PTR_IXY_d],z
ora #%00100000
sta REG_L
; FALLTROUGH
Z80_common_set_4567:
sta [PTR_IXY_d],z
jmp ZVM_next
Z80_illeg_xDCB_F0: +Z80_SET6_VIA_IXY_d_REGn REG_B ; SET 6,(IXY+d),B
Z80_illeg_xDCB_F1: +Z80_SET6_VIA_IXY_d_REGn REG_C ; SET 6,(IXY+d),C
Z80_illeg_xDCB_F2: +Z80_SET6_VIA_IXY_d_REGn REG_D ; SET 6,(IXY+d),D
Z80_illeg_xDCB_F3: +Z80_SET6_VIA_IXY_d_REGn REG_E ; SET 6,(IXY+d),E
Z80_illeg_xDCB_F4: +Z80_SET6_VIA_IXY_d_REGn REG_H ; SET 6,(IXY+d),H
Z80_illeg_xDCB_F5: +Z80_SET6_VIA_IXY_d_REGn REG_L ; SET 6,(IXY+d),L
Z80_illeg_xDCB_F8: +Z80_SET7_VIA_IXY_d_REGn REG_B ; SET 7,(IXY+d),B
Z80_illeg_xDCB_F9: +Z80_SET7_VIA_IXY_d_REGn REG_C ; SET 7,(IXY+d),C
Z80_illeg_xDCB_FA: +Z80_SET7_VIA_IXY_d_REGn REG_D ; SET 7,(IXY+d),D
Z80_illeg_xDCB_FB: +Z80_SET7_VIA_IXY_d_REGn REG_E ; SET 7,(IXY+d),E
Z80_illeg_xDCB_FC: +Z80_SET7_VIA_IXY_d_REGn REG_H ; SET 7,(IXY+d),H
Z80_illeg_xDCB_FD: +Z80_SET7_VIA_IXY_d_REGn REG_L ; SET 7,(IXY+d),L
; XXX turn code below into macros, rework remaining ones to use same concept
Z80_illeg_xDCB_87: ; RES 0,(IXY+d),A
lda [PTR_IXY_d],z
and #%11111110
bra Z80_common_setres_A
Z80_illeg_xDCB_8F: ; RES 1,(IXY+d),A
lda [PTR_IXY_d],z
and #%11111101
bra Z80_common_setres_A
Z80_illeg_xDCB_97: ; RES 2,(IXY+d),A
lda [PTR_IXY_d],z
and #%11111011
bra Z80_common_setres_A
Z80_illeg_xDCB_9F: ; RES 3,(IXY+d),A
lda [PTR_IXY_d],z
and #%11110111
bra Z80_common_setres_A
Z80_illeg_xDCB_A7: ; RES 4,(IXY+d),A
lda [PTR_IXY_d],z
and #%11101111
bra Z80_common_setres_A
Z80_illeg_xDCB_AF: ; RES 5,(IXY+d),A
lda [PTR_IXY_d],z
and #%11011111
bra Z80_common_setres_A
Z80_illeg_xDCB_B7: ; RES 6,(IXY+d),A
lda [PTR_IXY_d],z
and #%10111111
bra Z80_common_setres_A
Z80_illeg_xDCB_BF: ; RES 7,(IXY+d),A
lda [PTR_IXY_d],z
and #%01111111
bra Z80_common_setres_A
Z80_illeg_xDCB_C7: ; SET 0,(IXY+d),A
lda [PTR_IXY_d],z
ora #%00000001
bra Z80_common_setres_A
Z80_illeg_xDCB_CF: ; SET 1,(IXY+d),A
lda [PTR_IXY_d],z
ora #%00000010
bra Z80_common_setres_A
Z80_illeg_xDCB_D7: ; SET 2,(IXY+d),A
lda [PTR_IXY_d],z
ora #%00000100
bra Z80_common_setres_A
Z80_illeg_xDCB_DF: ; SET 3,(IXY+d),A
lda [PTR_IXY_d],z
ora #%00001000
bra Z80_common_setres_A
Z80_illeg_xDCB_E7: ; SET 4,(IXY+d),A
lda [PTR_IXY_d],z
ora #%00010000
bra Z80_common_setres_A
Z80_illeg_xDCB_EF: ; SET 5,(IXY+d),A
lda [PTR_IXY_d],z
ora #%00100000
bra Z80_common_setres_A
Z80_illeg_xDCB_F7: ; SET 6,(IXY+d),A
lda [PTR_IXY_d],z
ora #%01000000
bra Z80_common_setres_A
Z80_illeg_xDCB_FF: ; SET 7,(IXY+d),A
lda [PTR_IXY_d],z
ora #%10000000
; FALLTROUGH
Z80_common_setres_A:
sta REG_A
sta [PTR_IXY_d],z
jmp ZVM_next
src/zvm_m65/z80_instr_block.s
+67
View File
@@ -2,3 +2,70 @@
;
; Z80 block processing and search instructions
;
Z80_instr_ED_A0: ; LDI
lda REG_F
and #($FF - Z80_HF - Z80_PF - Z80_NF)
sta REG_F
jsr (VEC_fetch_via_HL)
jsr (VEC_store_via_DE)
inw REG_HL
inw REG_DE
dew REG_BC
+beq ZVM_next
+Z80_PUT_1_VF
jmp ZVM_next
Z80_instr_ED_B0: ; LDIR
lda REG_F
and #($FF - Z80_HF - Z80_PF - Z80_NF)
sta REG_F
@1:
jsr (VEC_fetch_via_HL)
jsr (VEC_store_via_DE)
inw REG_HL
inw REG_DE
dew REG_BC
bne @1
jmp ZVM_next
Z80_instr_ED_A8: ; LDD
lda REG_F
and #($FF - Z80_HF - Z80_PF - Z80_NF)
sta REG_F
jsr (VEC_fetch_via_HL)
jsr (VEC_store_via_DE)
dew REG_HL
dew REG_DE
dew REG_BC
+beq ZVM_next
+Z80_PUT_1_VF
jmp ZVM_next
Z80_instr_ED_B8: ; LDDR
lda REG_F
and #($FF - Z80_HF - Z80_PF - Z80_NF)
sta REG_F
@1:
jsr (VEC_fetch_via_HL)
jsr (VEC_store_via_DE)
dew REG_HL
dew REG_DE
dew REG_BC
bne @1
jmp ZVM_next
src/zvm_m65/z80_instr_exchange.s
+15
View File
@@ -65,3 +65,18 @@ Z80_instr_D9: ; EXX
stx REG_L_SH
jmp ZVM_next
!macro Z80_EX_VIA_SP_REGnn .REGnn {
lda .REGnn+0
jsr (VEC_xchng_stack_lo)
sta .REGnn+0
lda .REGnn+1
jsr (VEC_xchng_stack_hi)
sta .REGnn+1
jmp ZVM_next
}
Z80_instr_E3: +Z80_EX_VIA_SP_REGnn REG_HL ; EX (SP),HL
Z80_instr_DD_E3: +Z80_EX_VIA_SP_REGnn REG_IX ; EX (SP),IX
Z80_instr_FD_E3: +Z80_EX_VIA_SP_REGnn REG_IY ; EX (SP),IY
src/zvm_m65/z80_instr_load_16bit.s
+45 -1
View File
@@ -19,6 +19,50 @@ Z80_instr_31: +Z80_LD_REGnn_nn REG_SP ;
Z80_instr_DD_21: +Z80_LD_REGnn_nn REG_IX ; LD IX,nn
Z80_instr_FD_21: +Z80_LD_REGnn_nn REG_IY ; LD IY,nn
!macro Z80_LD_REGnn_REGnn .REGnn1, .REGnn2 {
lda .REGnn2+0
sta .REGnn1+0
jsr .REGnn2+1
sta .REGnn1+1
jmp ZVM_next
}
Z80_instr_F9: +Z80_LD_REGnn_REGnn REG_SP, REG_HL ; LD SP,HL
Z80_instr_DD_F9: +Z80_LD_REGnn_REGnn REG_SP, REG_IX ; LD SP,IX
Z80_instr_FD_F9: +Z80_LD_REGnn_REGnn REG_SP, REG_IY ; LD SP,IY
!macro Z80_LD_VIA_nn_REGnn .REGnn {
lda .REGnn+0
jsr (VEC_store_via_nn)
lda .REGnn+1
jsr (VEC_store_via_plus1)
jmp ZVM_next
}
Z80_illeg_ED_63: ; LD (nn),HL
Z80_instr_22: +Z80_LD_VIA_nn_REGnn REG_HL ; LD (nn),HL
Z80_instr_ED_43: +Z80_LD_VIA_nn_REGnn REG_BC ; LD (nn),BC
Z80_instr_ED_53: +Z80_LD_VIA_nn_REGnn REG_DE ; LD (nn),DE
Z80_instr_DD_22: +Z80_LD_VIA_nn_REGnn REG_IX ; LD (nn),IX
Z80_instr_FD_22: +Z80_LD_VIA_nn_REGnn REG_IY ; LD (nn),IY
Z80_instr_ED_73: +Z80_LD_VIA_nn_REGnn REG_SP ; LD (nn),SP
!macro Z80_LD_REGnn_VIA_nn .REGnn {
jsr (VEC_fetch_via_nn)
sta .REGnn+0
jsr (VEC_fetch_via_plus1)
sta .REGnn+1
jmp ZVM_next
}
Z80_illeg_ED_6B: ; LD HL,(nn)
Z80_instr_2A: +Z80_LD_REGnn_VIA_nn REG_HL ; LD HL,(nn)
Z80_instr_ED_4B: +Z80_LD_REGnn_VIA_nn REG_BC ; LD BC,(nn)
Z80_instr_ED_5B: +Z80_LD_REGnn_VIA_nn REG_DE ; LD DE,(nn)
Z80_instr_DD_2A: +Z80_LD_REGnn_VIA_nn REG_IX ; LD IX,(nn)
Z80_instr_FD_2A: +Z80_LD_REGnn_VIA_nn REG_IY ; LD IY,(nn)
Z80_instr_ED_7B: +Z80_LD_REGnn_VIA_nn REG_SP ; LD SP,(nn)
!macro Z80_PUSH_REGnn .REGnn {
lda .REGnn+1
jsr (VEC_store_stack)
@@ -47,4 +91,4 @@ Z80_instr_D1: +Z80_POP_REGnn REG_DE ;
Z80_instr_E1: +Z80_POP_REGnn REG_HL ; POP HL
Z80_instr_F1: +Z80_POP_REGnn REG_AF ; POP AF
Z80_instr_DD_E1: +Z80_POP_REGnn REG_IX ; POP IX
Z80_instr_FD_E1: +Z80_POP_REGnn REG_IY ; POP IY
Z80_instr_FD_E1: +Z80_POP_REGnn REG_IY ; POP IY
src/zvm_m65/z80_table_gen.s
+2
View File
@@ -0,0 +1,2 @@
; XXX: move ALL table generation here, for some tables (DAA) use floor/ceiling RAM
src/zvm_m65/zvm_core.s
+25 -148
View File
@@ -80,7 +80,18 @@ ZVM_store_next:
; unsupported illegal instructions
Z80_unsupported:
; XXX add a separate handler for illegal instructions
; XXX add a separate handler to warn about illegal instructions
; block I/O transfer - not implemented for now XXX implement them
Z80_instr_ED_A2: ; INI
Z80_instr_ED_B2: ; INIR
Z80_instr_ED_AA: ; IND
Z80_instr_ED_BA: ; INDR
Z80_instr_ED_A3: ; OUTI
Z80_instr_ED_B3: ; OTIR
Z80_instr_ED_AB: ; OUTD
Z80_instr_ED_BB: ; OTDR
; XXX add a separate handler to warn about them
; LD instructions with no effect
Z80_instr_40: ; LD B,B
Z80_instr_49: ; LD C,C
@@ -93,7 +104,7 @@ Z80_illeg_DD_64: ;
Z80_illeg_DD_6D: ; LD IXL,IXL
Z80_illeg_FD_64: ; LD IYH,IYH
Z80_illeg_FD_6D: ; LD IYL,IYL
; For interrupts (emulation not needed for CP/M)
; Instructions needed only for interrupts (emulation not needed for CP/M)
Z80_instr_ED_46: ; IM 0
Z80_illeg_ED_4E: ; IM 0
Z80_illeg_ED_66: ; IM 0
@@ -102,12 +113,13 @@ Z80_instr_ED_56: ;
Z80_illeg_ED_76: ; IM 1
Z80_instr_ED_5E: ; IM 2
Z80_illeg_ED_7E: ; IM 2
; Real NOP
; NOP
Z80_instr_00: ; NOP
Z80_illeg_ED_77: ; NOP
Z80_illeg_ED_7F: ; NOP
; Dispatch via jumptable
; Fetch and execute the next instruction
ZVM_next: +ZVM_DISPATCH Z80_vectab_0, Z80_vectab_1
; Dispatch via jumptable
Z80_instr_CB: +ZVM_DISPATCH Z80_vectab_CB_0, Z80_vectab_CB_1 ; #CB
Z80_instr_DD: +ZVM_DISPATCH Z80_vectab_DD_0, Z80_vectab_DD_1 ; #DD
Z80_instr_ED: +ZVM_DISPATCH Z80_vectab_ED_0, Z80_vectab_ED_1 ; #ED
@@ -116,6 +128,14 @@ Z80_instr_FD: +ZVM_DISPATCH Z80_vectab_FD_0, Z80_vectab_FD_1 ;
; XXX addition and subtraction are slow; pre-calculate data/flag tables in the extended 8MB RAM
; XXX use TRB/TSB instead of LDA + AND/ORA + STA when applicable
@@ -132,12 +152,8 @@ Z80_instr_DD_CB: ; #DDCB
Z80_instr_FD_CB: ; #FDCB
Z80_instr_09: ; ADD HL,BC
Z80_instr_19: ; ADD HL,DE
Z80_instr_22: ; LD (nn),HL
Z80_instr_29: ; ADD HL,HL
Z80_instr_2A: ; LD HL,(nn)
Z80_instr_39: ; ADD HL,SP
Z80_instr_E3: ; EX (SP),HL
Z80_instr_F9: ; LD SP,HL
Z80_instr_CB_06: ; RLC (HL)
Z80_instr_CB_0E: ; RRC (HL)
Z80_instr_CB_16: ; RL (HL)
@@ -147,52 +163,26 @@ Z80_instr_CB_2E: ; SRA (HL)
Z80_instr_CB_3E: ; SRL (HL)
Z80_instr_DD_09: ; ADD IX,BC
Z80_instr_DD_19: ; ADD IX,DE
Z80_instr_DD_22: ; LD (nn),IX
Z80_instr_DD_29: ; ADD IX,IX
Z80_instr_DD_2A: ; LD IX,(nn)
Z80_instr_DD_39: ; ADD IX,SP
Z80_instr_DD_E3: ; EX (SP),IX
Z80_instr_DD_F9: ; LD SP,IX
Z80_instr_ED_42: ; SBC HL,BC
Z80_instr_ED_43: ; LD (nn),BC
Z80_instr_ED_4A: ; ADC HL,BC
Z80_instr_ED_4B: ; LD BC,(nn)
Z80_instr_ED_52: ; SBC HL,DE
Z80_instr_ED_53: ; LD (nn),DE
Z80_instr_ED_5A: ; ADC HL,DE
Z80_instr_ED_5B: ; LD DE,(nn)
Z80_instr_ED_62: ; SBC HL,HL
Z80_instr_ED_67: ; RRD
Z80_instr_ED_6A: ; ADC HL,HL
Z80_instr_ED_6F: ; RLD
Z80_instr_ED_72: ; SBC HL,SP
Z80_instr_ED_73: ; LD (nn),SP
Z80_instr_ED_7A: ; ADC HL,SP
Z80_instr_ED_7B: ; LD SP,(nn)
Z80_instr_ED_A0: ; LDI
Z80_instr_ED_A1: ; CPI
Z80_instr_ED_A2: ; INI
Z80_instr_ED_A3: ; OUTI
Z80_instr_ED_A8: ; LDD
Z80_instr_ED_A9: ; CPD
Z80_instr_ED_AA: ; IND
Z80_instr_ED_AB: ; OUTD
Z80_instr_ED_B0: ; LDIR
Z80_instr_ED_B1: ; CPIR
Z80_instr_ED_B2: ; INIR
Z80_instr_ED_B3: ; OTIR
Z80_instr_ED_B8: ; LDDR
Z80_instr_ED_B9: ; CPDR
Z80_instr_ED_BA: ; INDR
Z80_instr_ED_BB: ; OTDR
Z80_instr_FD_09: ; ADD IY,BC
Z80_instr_FD_19: ; ADD IY,DE
Z80_instr_FD_22: ; LD (nn),IY
Z80_instr_FD_29: ; ADD IY,IY
Z80_instr_FD_2A: ; LD IY,(nn)
Z80_instr_FD_39: ; ADD IY,SP
Z80_instr_FD_E3: ; EX (SP),IY
Z80_instr_FD_F9: ; LD SP,IY
Z80_instr_xDCB_06: ; RLC (IXY+d)
Z80_instr_xDCB_0E: ; RRC (IXY+d)
Z80_instr_xDCB_16: ; RL (IXY+d)
@@ -203,8 +193,6 @@ Z80_instr_xDCB_3E: ; SRL (IXY+d)
Z80_illeg_CB_36: ; SLL (HL)
Z80_illeg_ED_70: ; IN F,(C)
Z80_illeg_ED_71: ; OUT (C),0
Z80_illeg_ED_63: ; LD (nn),HL
Z80_illeg_ED_6B: ; LD HL,(nn)
Z80_illeg_xDCB_00: ; RLC (IXY+d),B
Z80_illeg_xDCB_01: ; RLC (IXY+d),C
Z80_illeg_xDCB_02: ; RLC (IXY+d),D
@@ -262,118 +250,7 @@ Z80_illeg_xDCB_3B: ; SLR (IXY+d),E
Z80_illeg_xDCB_3C: ; SLR (IXY+d),H
Z80_illeg_xDCB_3D: ; SLR (IXY+d),L
Z80_illeg_xDCB_3F: ; SLR (IXY+d),A
Z80_illeg_xDCB_80: ; RES 0,(IXY+d),B
Z80_illeg_xDCB_81: ; RES 0,(IXY+d),C
Z80_illeg_xDCB_82: ; RES 0,(IXY+d),D
Z80_illeg_xDCB_83: ; RES 0,(IXY+d),E
Z80_illeg_xDCB_84: ; RES 0,(IXY+d),H
Z80_illeg_xDCB_85: ; RES 0,(IXY+d),L
Z80_illeg_xDCB_87: ; RES 0,(IXY+d),A
Z80_illeg_xDCB_88: ; RES 1,(IXY+d),B
Z80_illeg_xDCB_89: ; RES 1,(IXY+d),C
Z80_illeg_xDCB_8A: ; RES 1,(IXY+d),D
Z80_illeg_xDCB_8B: ; RES 1,(IXY+d),E
Z80_illeg_xDCB_8C: ; RES 1,(IXY+d),H
Z80_illeg_xDCB_8D: ; RES 1,(IXY+d),L
Z80_illeg_xDCB_8F: ; RES 1,(IXY+d),A
Z80_illeg_xDCB_90: ; RES 2,(IXY+d),B
Z80_illeg_xDCB_91: ; RES 2,(IXY+d),C
Z80_illeg_xDCB_92: ; RES 2,(IXY+d),D
Z80_illeg_xDCB_93: ; RES 2,(IXY+d),E
Z80_illeg_xDCB_94: ; RES 2,(IXY+d),H
Z80_illeg_xDCB_95: ; RES 2,(IXY+d),L
Z80_illeg_xDCB_97: ; RES 2,(IXY+d),A
Z80_illeg_xDCB_98: ; RES 3,(IXY+d),B
Z80_illeg_xDCB_99: ; RES 3,(IXY+d),C
Z80_illeg_xDCB_9A: ; RES 3,(IXY+d),D
Z80_illeg_xDCB_9B: ; RES 3,(IXY+d),E
Z80_illeg_xDCB_9C: ; RES 3,(IXY+d),H
Z80_illeg_xDCB_9D: ; RES 3,(IXY+d),L
Z80_illeg_xDCB_9F: ; RES 3,(IXY+d),A
Z80_illeg_xDCB_A0: ; RES 4,(IXY+d),B
Z80_illeg_xDCB_A1: ; RES 4,(IXY+d),C
Z80_illeg_xDCB_A2: ; RES 4,(IXY+d),D
Z80_illeg_xDCB_A3: ; RES 4,(IXY+d),E
Z80_illeg_xDCB_A4: ; RES 4,(IXY+d),H
Z80_illeg_xDCB_A5: ; RES 4,(IXY+d),L
Z80_illeg_xDCB_A7: ; RES 4,(IXY+d),A
Z80_illeg_xDCB_A8: ; RES 5,(IXY+d),B
Z80_illeg_xDCB_A9: ; RES 5,(IXY+d),C
Z80_illeg_xDCB_AA: ; RES 5,(IXY+d),D
Z80_illeg_xDCB_AB: ; RES 5,(IXY+d),E
Z80_illeg_xDCB_AC: ; RES 5,(IXY+d),H
Z80_illeg_xDCB_AD: ; RES 5,(IXY+d),L
Z80_illeg_xDCB_AF: ; RES 5,(IXY+d),A
Z80_illeg_xDCB_B0: ; RES 6,(IXY+d),B
Z80_illeg_xDCB_B1: ; RES 6,(IXY+d),C
Z80_illeg_xDCB_B2: ; RES 6,(IXY+d),D
Z80_illeg_xDCB_B3: ; RES 6,(IXY+d),E
Z80_illeg_xDCB_B4: ; RES 6,(IXY+d),H
Z80_illeg_xDCB_B5: ; RES 6,(IXY+d),L
Z80_illeg_xDCB_B7: ; RES 6,(IXY+d),A
Z80_illeg_xDCB_B8: ; RES 7,(IXY+d),B
Z80_illeg_xDCB_B9: ; RES 7,(IXY+d),C
Z80_illeg_xDCB_BA: ; RES 7,(IXY+d),D
Z80_illeg_xDCB_BB: ; RES 7,(IXY+d),E
Z80_illeg_xDCB_BC: ; RES 7,(IXY+d),H
Z80_illeg_xDCB_BD: ; RES 7,(IXY+d),L
Z80_illeg_xDCB_BF: ; RES 7,(IXY+d),A
Z80_illeg_xDCB_C0: ; SET 0,(IXY+d),B
Z80_illeg_xDCB_C1: ; SET 0,(IXY+d),C
Z80_illeg_xDCB_C2: ; SET 0,(IXY+d),D
Z80_illeg_xDCB_C3: ; SET 0,(IXY+d),E
Z80_illeg_xDCB_C4: ; SET 0,(IXY+d),H
Z80_illeg_xDCB_C5: ; SET 0,(IXY+d),L
Z80_illeg_xDCB_C7: ; SET 0,(IXY+d),A
Z80_illeg_xDCB_C8: ; SET 1,(IXY+d),B
Z80_illeg_xDCB_C9: ; SET 1,(IXY+d),C
Z80_illeg_xDCB_CA: ; SET 1,(IXY+d),D
Z80_illeg_xDCB_CB: ; SET 1,(IXY+d),E
Z80_illeg_xDCB_CC: ; SET 1,(IXY+d),H
Z80_illeg_xDCB_CD: ; SET 1,(IXY+d),L
Z80_illeg_xDCB_CF: ; SET 1,(IXY+d),A
Z80_illeg_xDCB_D0: ; SET 2,(IXY+d),B
Z80_illeg_xDCB_D1: ; SET 2,(IXY+d),C
Z80_illeg_xDCB_D2: ; SET 2,(IXY+d),D
Z80_illeg_xDCB_D3: ; SET 2,(IXY+d),E
Z80_illeg_xDCB_D4: ; SET 2,(IXY+d),H
Z80_illeg_xDCB_D5: ; SET 2,(IXY+d),L
Z80_illeg_xDCB_D7: ; SET 2,(IXY+d),A
Z80_illeg_xDCB_D8: ; SET 3,(IXY+d),B
Z80_illeg_xDCB_D9: ; SET 3,(IXY+d),C
Z80_illeg_xDCB_DA: ; SET 3,(IXY+d),D
Z80_illeg_xDCB_DB: ; SET 3,(IXY+d),E
Z80_illeg_xDCB_DC: ; SET 3,(IXY+d),H
Z80_illeg_xDCB_DD: ; SET 3,(IXY+d),L
Z80_illeg_xDCB_DF: ; SET 3,(IXY+d),A
Z80_illeg_xDCB_E0: ; SET 4,(IXY+d),B
Z80_illeg_xDCB_E1: ; SET 4,(IXY+d),C
Z80_illeg_xDCB_E2: ; SET 4,(IXY+d),D
Z80_illeg_xDCB_E3: ; SET 4,(IXY+d),E
Z80_illeg_xDCB_E4: ; SET 4,(IXY+d),H
Z80_illeg_xDCB_E5: ; SET 4,(IXY+d),L
Z80_illeg_xDCB_E7: ; SET 4,(IXY+d),A
Z80_illeg_xDCB_E8: ; SET 5,(IXY+d),B
Z80_illeg_xDCB_E9: ; SET 5,(IXY+d),C
Z80_illeg_xDCB_EA: ; SET 5,(IXY+d),D
Z80_illeg_xDCB_EB: ; SET 5,(IXY+d),E
Z80_illeg_xDCB_EC: ; SET 5,(IXY+d),H
Z80_illeg_xDCB_ED: ; SET 5,(IXY+d),L
Z80_illeg_xDCB_EF: ; SET 5,(IXY+d),A
Z80_illeg_xDCB_F0: ; SET 6,(IXY+d),B
Z80_illeg_xDCB_F1: ; SET 6,(IXY+d),C
Z80_illeg_xDCB_F2: ; SET 6,(IXY+d),D
Z80_illeg_xDCB_F3: ; SET 6,(IXY+d),E
Z80_illeg_xDCB_F4: ; SET 6,(IXY+d),H
Z80_illeg_xDCB_F5: ; SET 6,(IXY+d),L
Z80_illeg_xDCB_F7: ; SET 6,(IXY+d),A
Z80_illeg_xDCB_F8: ; SET 7,(IXY+d),B
Z80_illeg_xDCB_F9: ; SET 7,(IXY+d),C
Z80_illeg_xDCB_FA: ; SET 7,(IXY+d),D
Z80_illeg_xDCB_FB: ; SET 7,(IXY+d),E
Z80_illeg_xDCB_FC: ; SET 7,(IXY+d),H
Z80_illeg_xDCB_FD: ; SET 7,(IXY+d),L
Z80_illeg_xDCB_FF: ; SET 7,(IXY+d),A
jmp ZVM_next ; XXX provide implementation