more work on Z80 opcodes
This commit is contained in:
FeralChild64 authored and FeralChild64 committed
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21d3c8758b
commit
83bcbcd5e0
8 files changed
+754
-715
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@@ -22,7 +22,11 @@
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!addr REG_H_SH = $11
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!addr REG_IX = $12 ; 16-bit index register
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!addr REG_IXL = $12
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!addr REG_IXH = $13
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!addr REG_IY = $14 ; 16-bit index register
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!addr REG_IYL = $14
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!addr REG_IYH = $15
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!addr REG_SP = $16 ; 16-bit stack pointer
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!addr REG_PC = $18 ; 16-bit program counter
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@@ -49,14 +53,20 @@
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!addr VEC_fetch_value = $60
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!addr VEC_fetch_stack = $62
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!addr VEC_store_stack = $64
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!addr VEC_fetch_via_HL = $66
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!addr VEC_store_via_HL = $68
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!addr VEC_fetch_via_IX_d = $6A
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!addr VEC_fetch_via_IY_d = $6C
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!addr VEC_store_via_IX_d = $6E
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!addr VEC_store_via_IY_d = $70
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!addr VEC_fetch_via_nn = $72
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!addr VEC_store_via_nn = $74
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!addr VEC_fetch_via_BC = $66 ; XXX add routines
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!addr VEC_store_via_BC = $68 ; XXX add routines
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!addr VEC_fetch_via_DE = $6A ; XXX add routines
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!addr VEC_store_via_DE = $6C ; XXX add routines
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!addr VEC_fetch_via_HL = $6E
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!addr VEC_store_via_HL = $70
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!addr VEC_fetch_via_IX_d = $72
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!addr VEC_fetch_via_IY_d = $74
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!addr VEC_store_via_IX_d = $76
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!addr VEC_store_via_IY_d = $78
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!addr VEC_fetch_via_nn = $7A
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!addr VEC_store_via_nn = $7C
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; Masks for Z80 flag (F) register
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+120
-120
@@ -117,69 +117,69 @@ Z80_vectab_CB_1:
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Z80_vectab_DD_0:
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!word Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD
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!word Z80_illegal__DD, Z80_instr_DD_09, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD
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!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
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!word Z80_unsupported, Z80_instr_DD_09, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
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!word Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD
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!word Z80_illegal__DD, Z80_instr_DD_19, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD
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!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
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!word Z80_unsupported, Z80_instr_DD_19, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
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!word Z80_illegal__DD, Z80_instr_DD_21, Z80_instr_DD_22, Z80_instr_DD_23, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD
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!word Z80_illegal__DD, Z80_instr_DD_29, Z80_instr_DD_2A, Z80_instr_DD_2B, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD
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!word Z80_unsupported, Z80_instr_DD_21, Z80_instr_DD_22, Z80_instr_DD_23, Z80_illeg_DD_24, Z80_illeg_DD_25, Z80_illeg_DD_26, Z80_unsupported
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!word Z80_unsupported, Z80_instr_DD_29, Z80_instr_DD_2A, Z80_instr_DD_2B, Z80_illeg_DD_2C, Z80_illeg_DD_2D, Z80_illeg_DD_2E, Z80_unsupported
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!word Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_instr_DD_34, Z80_instr_DD_35, Z80_illegal__DD, Z80_illegal__DD
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!word Z80_illegal__DD, Z80_instr_DD_39, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD
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!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_instr_DD_34, Z80_instr_DD_35, Z80_unsupported, Z80_unsupported
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!word Z80_unsupported, Z80_instr_DD_39, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
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!word Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_instr_DD_46, Z80_illegal__DD
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!word Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_instr_DD_4E, Z80_illegal__DD
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!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_illeg_DD_44, Z80_illeg_DD_45, Z80_instr_DD_46, Z80_unsupported
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!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_illeg_DD_4C, Z80_illeg_DD_4D, Z80_instr_DD_4E, Z80_unsupported
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!word Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_instr_DD_56, Z80_illegal__DD
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!word Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_instr_DD_5E, Z80_illegal__DD
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!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_illeg_DD_54, Z80_illeg_DD_55, Z80_instr_DD_56, Z80_unsupported
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!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_illeg_DD_5C, Z80_illeg_DD_5D, Z80_instr_DD_5E, Z80_unsupported
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!word Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_instr_DD_66, Z80_illegal__DD
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!word Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_instr_DD_6E, Z80_illegal__DD
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!word Z80_illeg_DD_60, Z80_illeg_DD_61, Z80_illeg_DD_62, Z80_illeg_DD_63, Z80_illeg_DD_64, Z80_illeg_DD_65, Z80_instr_DD_66, Z80_illeg_DD_67
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!word Z80_illeg_DD_68, Z80_illeg_DD_69, Z80_illeg_DD_6A, Z80_illeg_DD_6B, Z80_illeg_DD_6C, Z80_illeg_DD_6D, Z80_instr_DD_6E, Z80_illeg_DD_6F
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!word Z80_instr_DD_70, Z80_instr_DD_71, Z80_instr_DD_72, Z80_instr_DD_73, Z80_instr_DD_74, Z80_instr_DD_75, Z80_illegal__DD, Z80_instr_DD_77
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!word Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_instr_DD_7E, Z80_illegal__DD
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!word Z80_instr_DD_70, Z80_instr_DD_71, Z80_instr_DD_72, Z80_instr_DD_73, Z80_instr_DD_74, Z80_instr_DD_75, Z80_unsupported, Z80_instr_DD_77
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!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_illeg_DD_7C, Z80_illeg_DD_7D, Z80_instr_DD_7E, Z80_unsupported
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Z80_vectab_DD_1:
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!word Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_instr_DD_86, Z80_illegal__DD
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!word Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_instr_DD_8E, Z80_illegal__DD
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!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_illeg_DD_84, Z80_illeg_DD_85, Z80_instr_DD_86, Z80_unsupported
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!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_illeg_DD_8C, Z80_illeg_DD_8D, Z80_instr_DD_8E, Z80_unsupported
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!word Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_instr_DD_96, Z80_illegal__DD
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!word Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_instr_DD_9E, Z80_illegal__DD
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!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_illeg_DD_94, Z80_illeg_DD_95, Z80_instr_DD_96, Z80_unsupported
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!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_illeg_DD_9C, Z80_illeg_DD_9D, Z80_instr_DD_9E, Z80_unsupported
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!word Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_instr_DD_A6, Z80_illegal__DD
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!word Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_instr_DD_AE, Z80_illegal__DD
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!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_illeg_DD_A4, Z80_illeg_DD_A5, Z80_instr_DD_A6, Z80_unsupported
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!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_illeg_DD_AC, Z80_illeg_DD_AD, Z80_instr_DD_AE, Z80_unsupported
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!word Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_instr_DD_B6, Z80_illegal__DD
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!word Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_instr_DD_BE, Z80_illegal__DD
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!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_illeg_DD_B4, Z80_illeg_DD_B5, Z80_instr_DD_B6, Z80_unsupported
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!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_illeg_DD_BC, Z80_illeg_DD_BD, Z80_instr_DD_BE, Z80_unsupported
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!word Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD
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!word Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_instr_DD_CB, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD
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!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
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!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_instr_DD_CB, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
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!word Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD
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!word Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD
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!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
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!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
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!word Z80_illegal__DD, Z80_instr_DD_E1, Z80_illegal__DD, Z80_instr_DD_E3, Z80_illegal__DD, Z80_instr_DD_E5, Z80_illegal__DD, Z80_illegal__DD
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!word Z80_illegal__DD, Z80_instr_DD_E9, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD
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!word Z80_unsupported, Z80_instr_DD_E1, Z80_unsupported, Z80_instr_DD_E3, Z80_unsupported, Z80_instr_DD_E5, Z80_unsupported, Z80_unsupported
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!word Z80_unsupported, Z80_instr_DD_E9, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
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!word Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD
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!word Z80_illegal__DD, Z80_instr_DD_F9, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD
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!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
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!word Z80_unsupported, Z80_instr_DD_F9, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
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Z80_vectab_ED_0:
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!word Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED
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!word Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED
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!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
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!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
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!word Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED
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!word Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED
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!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
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!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
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!word Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED
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!word Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED
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!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
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!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
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!word Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED
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!word Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED
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!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
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!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
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!word Z80_instr_ED_40, Z80_instr_ED_41, Z80_instr_ED_42, Z80_instr_ED_43, Z80_instr_ED_44, Z80_instr_ED_45, Z80_instr_ED_46, Z80_instr_ED_47
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!word Z80_instr_ED_48, Z80_instr_ED_49, Z80_instr_ED_4A, Z80_instr_ED_4B, Z80_illeg_ED_4C, Z80_instr_ED_4D, Z80_illeg_ED_4E, Z80_instr_ED_4F
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@@ -187,138 +187,138 @@ Z80_vectab_ED_0:
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!word Z80_instr_ED_50, Z80_instr_ED_51, Z80_instr_ED_52, Z80_instr_ED_53, Z80_illeg_ED_54, Z80_illeg_ED_55, Z80_instr_ED_56, Z80_instr_ED_57
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!word Z80_instr_ED_58, Z80_instr_ED_59, Z80_instr_ED_5A, Z80_instr_ED_5B, Z80_illeg_ED_5C, Z80_illeg_ED_5D, Z80_instr_ED_5E, Z80_instr_ED_5F
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!word Z80_instr_ED_60, Z80_instr_ED_61, Z80_instr_ED_62, Z80_illegal__ED, Z80_illeg_ED_64, Z80_illeg_ED_65, Z80_illeg_ED_66, Z80_instr_ED_67
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!word Z80_instr_ED_68, Z80_instr_ED_69, Z80_instr_ED_6A, Z80_illegal__ED, Z80_illeg_ED_6C, Z80_illeg_ED_6D, Z80_illeg_ED_6E, Z80_instr_ED_6F
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!word Z80_instr_ED_60, Z80_instr_ED_61, Z80_instr_ED_62, Z80_illeg_ED_63, Z80_illeg_ED_64, Z80_illeg_ED_65, Z80_illeg_ED_66, Z80_instr_ED_67
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!word Z80_instr_ED_68, Z80_instr_ED_69, Z80_instr_ED_6A, Z80_illeg_ED_6B, Z80_illeg_ED_6C, Z80_illeg_ED_6D, Z80_illeg_ED_6E, Z80_instr_ED_6F
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!word Z80_illeg_ED_70, Z80_illeg_ED_71, Z80_instr_ED_72, Z80_instr_ED_73, Z80_illeg_ED_74, Z80_illeg_ED_75, Z80_illeg_ED_76, Z80_illeg_ED_77
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!word Z80_instr_ED_78, Z80_instr_ED_79, Z80_instr_ED_7A, Z80_instr_ED_7B, Z80_illeg_ED_7C, Z80_illeg_ED_7D, Z80_illeg_ED_7E, Z80_illeg_ED_7F
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Z80_vectab_ED_1:
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!word Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED
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!word Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED
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!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
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!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
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!word Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED
|
||||
!word Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED
|
||||
!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
|
||||
!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
|
||||
|
||||
!word Z80_instr_ED_A0, Z80_instr_ED_A1, Z80_instr_ED_A2, Z80_instr_ED_A3, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED
|
||||
!word Z80_instr_ED_A8, Z80_instr_ED_A9, Z80_instr_ED_AA, Z80_instr_ED_AB, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED
|
||||
!word Z80_instr_ED_A0, Z80_instr_ED_A1, Z80_instr_ED_A2, Z80_instr_ED_A3, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
|
||||
!word Z80_instr_ED_A8, Z80_instr_ED_A9, Z80_instr_ED_AA, Z80_instr_ED_AB, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
|
||||
|
||||
!word Z80_instr_ED_B0, Z80_instr_ED_B1, Z80_instr_ED_B2, Z80_instr_ED_B3, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED
|
||||
!word Z80_instr_ED_B8, Z80_instr_ED_B9, Z80_instr_ED_BA, Z80_instr_ED_BB, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED
|
||||
!word Z80_instr_ED_B0, Z80_instr_ED_B1, Z80_instr_ED_B2, Z80_instr_ED_B3, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
|
||||
!word Z80_instr_ED_B8, Z80_instr_ED_B9, Z80_instr_ED_BA, Z80_instr_ED_BB, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
|
||||
|
||||
!word Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED
|
||||
!word Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED
|
||||
!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
|
||||
!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
|
||||
|
||||
!word Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED
|
||||
!word Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED
|
||||
!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
|
||||
!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
|
||||
|
||||
!word Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED
|
||||
!word Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED
|
||||
!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
|
||||
!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
|
||||
|
||||
!word Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED
|
||||
!word Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED
|
||||
!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
|
||||
!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
|
||||
|
||||
Z80_vectab_FD_0:
|
||||
|
||||
!word Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD
|
||||
!word Z80_illegal__FD, Z80_instr_FD_09, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD
|
||||
!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
|
||||
!word Z80_unsupported, Z80_instr_FD_09, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
|
||||
|
||||
!word Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD
|
||||
!word Z80_illegal__FD, Z80_instr_FD_19, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD
|
||||
!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
|
||||
!word Z80_unsupported, Z80_instr_FD_19, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
|
||||
|
||||
!word Z80_illegal__FD, Z80_instr_FD_21, Z80_instr_FD_22, Z80_instr_FD_23, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD
|
||||
!word Z80_illegal__FD, Z80_instr_FD_29, Z80_instr_FD_2A, Z80_instr_FD_2B, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD
|
||||
!word Z80_unsupported, Z80_instr_FD_21, Z80_instr_FD_22, Z80_instr_FD_23, Z80_illeg_FD_24, Z80_illeg_FD_25, Z80_illeg_FD_26, Z80_unsupported
|
||||
!word Z80_unsupported, Z80_instr_FD_29, Z80_instr_FD_2A, Z80_instr_FD_2B, Z80_illeg_FD_2C, Z80_illeg_FD_2D, Z80_illeg_FD_2E, Z80_unsupported
|
||||
|
||||
!word Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_instr_FD_34, Z80_instr_FD_35, Z80_illegal__FD, Z80_illegal__FD
|
||||
!word Z80_illegal__FD, Z80_instr_FD_39, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD
|
||||
!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_instr_FD_34, Z80_instr_FD_35, Z80_unsupported, Z80_unsupported
|
||||
!word Z80_unsupported, Z80_instr_FD_39, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
|
||||
|
||||
!word Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_instr_FD_46, Z80_illegal__FD
|
||||
!word Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_instr_FD_4E, Z80_illegal__FD
|
||||
!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_illeg_FD_44, Z80_illeg_FD_45, Z80_unsupported, Z80_unsupported
|
||||
!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_illeg_FD_4C, Z80_illeg_FD_4D, Z80_instr_FD_4E, Z80_unsupported
|
||||
|
||||
!word Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_instr_FD_56, Z80_illegal__FD
|
||||
!word Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_instr_FD_5E, Z80_illegal__FD
|
||||
!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_illeg_FD_54, Z80_illeg_FD_55, Z80_unsupported, Z80_unsupported
|
||||
!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_illeg_FD_5C, Z80_illeg_FD_5D, Z80_instr_FD_5E, Z80_unsupported
|
||||
|
||||
!word Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_instr_FD_66, Z80_illegal__FD
|
||||
!word Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_instr_FD_6E, Z80_illegal__FD
|
||||
!word Z80_illeg_FD_60, Z80_illeg_FD_61, Z80_illeg_FD_62, Z80_illeg_FD_63, Z80_illeg_FD_64, Z80_illeg_FD_65, Z80_instr_FD_66, Z80_illeg_FD_67
|
||||
!word Z80_illeg_FD_68, Z80_illeg_FD_69, Z80_illeg_FD_6A, Z80_illeg_FD_6B, Z80_illeg_FD_6C, Z80_illeg_FD_6D, Z80_instr_FD_6E, Z80_illeg_FD_6F
|
||||
|
||||
!word Z80_instr_FD_70, Z80_instr_FD_71, Z80_instr_FD_72, Z80_instr_FD_73, Z80_instr_FD_74, Z80_instr_FD_75, Z80_illegal__FD, Z80_instr_FD_77
|
||||
!word Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_instr_FD_7E, Z80_illegal__FD
|
||||
!word Z80_instr_FD_70, Z80_instr_FD_71, Z80_instr_FD_72, Z80_instr_FD_73, Z80_instr_FD_74, Z80_instr_FD_75, Z80_unsupported, Z80_instr_FD_77
|
||||
!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_illeg_FD_7C, Z80_illeg_FD_7D, Z80_instr_FD_7E, Z80_unsupported
|
||||
|
||||
Z80_vectab_FD_1:
|
||||
|
||||
!word Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_instr_FD_86, Z80_illegal__FD
|
||||
!word Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_instr_FD_8E, Z80_illegal__FD
|
||||
!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_illeg_FD_84, Z80_illeg_FD_85, Z80_instr_FD_86, Z80_unsupported
|
||||
!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_illeg_FD_8C, Z80_illeg_FD_8D, Z80_instr_FD_8E, Z80_unsupported
|
||||
|
||||
!word Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_instr_FD_96, Z80_illegal__FD
|
||||
!word Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_instr_FD_9E, Z80_illegal__FD
|
||||
!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_illeg_FD_94, Z80_illeg_FD_95, Z80_instr_FD_96, Z80_unsupported
|
||||
!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_illeg_FD_9C, Z80_illeg_FD_9D, Z80_instr_FD_9E, Z80_unsupported
|
||||
|
||||
!word Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_instr_FD_A6, Z80_illegal__FD
|
||||
!word Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_instr_FD_AE, Z80_illegal__FD
|
||||
!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_illeg_FD_A4, Z80_illeg_FD_A5, Z80_instr_FD_A6, Z80_unsupported
|
||||
!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_illeg_FD_AC, Z80_illeg_FD_AD, Z80_instr_FD_AE, Z80_unsupported
|
||||
|
||||
!word Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_instr_FD_B6, Z80_illegal__FD
|
||||
!word Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_instr_FD_BE, Z80_illegal__FD
|
||||
!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_illeg_FD_B4, Z80_illeg_FD_B5, Z80_instr_FD_B6, Z80_unsupported
|
||||
!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_illeg_FD_BC, Z80_illeg_FD_BD, Z80_instr_FD_BE, Z80_unsupported
|
||||
|
||||
!word Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD
|
||||
!word Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_instr_FD_CB, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD
|
||||
!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
|
||||
!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_instr_FD_CB, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
|
||||
|
||||
!word Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD
|
||||
!word Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD
|
||||
!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
|
||||
!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
|
||||
|
||||
!word Z80_illegal__FD, Z80_instr_FD_E1, Z80_illegal__FD, Z80_instr_FD_E3, Z80_illegal__FD, Z80_instr_FD_E5, Z80_illegal__FD, Z80_illegal__FD
|
||||
!word Z80_illegal__FD, Z80_instr_FD_E9, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD
|
||||
!word Z80_unsupported, Z80_instr_FD_E1, Z80_unsupported, Z80_instr_FD_E3, Z80_unsupported, Z80_instr_FD_E5, Z80_unsupported, Z80_unsupported
|
||||
!word Z80_unsupported, Z80_instr_FD_E9, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
|
||||
|
||||
!word Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD
|
||||
!word Z80_illegal__FD, Z80_instr_FD_F9, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD
|
||||
!word Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
|
||||
!word Z80_unsupported, Z80_instr_FD_F9, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported, Z80_unsupported
|
||||
|
||||
Z80_vectab_xDCB_0:
|
||||
|
||||
!word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_06, Z80_illegal__xDCB
|
||||
!word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_0E, Z80_illegal__xDCB
|
||||
!word Z80_illeg_xDCB_00, Z80_illeg_xDCB_01, Z80_illeg_xDCB_02, Z80_illeg_xDCB_03, Z80_illeg_xDCB_04, Z80_illeg_xDCB_05, Z80_instr_xDCB_06, Z80_illeg_xDCB_07
|
||||
!word Z80_illeg_xDCB_08, Z80_illeg_xDCB_09, Z80_illeg_xDCB_0A, Z80_illeg_xDCB_0B, Z80_illeg_xDCB_0C, Z80_illeg_xDCB_0D, Z80_instr_xDCB_0E, Z80_illeg_xDCB_0F
|
||||
|
||||
!word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_16, Z80_illegal__xDCB
|
||||
!word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_1E, Z80_illegal__xDCB
|
||||
!word Z80_illeg_xDCB_10, Z80_illeg_xDCB_11, Z80_illeg_xDCB_12, Z80_illeg_xDCB_13, Z80_illeg_xDCB_14, Z80_illeg_xDCB_15, Z80_instr_xDCB_16, Z80_illeg_xDCB_17
|
||||
!word Z80_illeg_xDCB_18, Z80_illeg_xDCB_19, Z80_illeg_xDCB_1A, Z80_illeg_xDCB_1B, Z80_illeg_xDCB_1C, Z80_illeg_xDCB_1D, Z80_instr_xDCB_1E, Z80_illeg_xDCB_1F
|
||||
|
||||
!word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_26, Z80_illegal__xDCB
|
||||
!word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_2E, Z80_illegal__xDCB
|
||||
!word Z80_illeg_xDCB_20, Z80_illeg_xDCB_21, Z80_illeg_xDCB_22, Z80_illeg_xDCB_23, Z80_illeg_xDCB_24, Z80_illeg_xDCB_25, Z80_instr_xDCB_26, Z80_illeg_xDCB_27
|
||||
!word Z80_illeg_xDCB_28, Z80_illeg_xDCB_29, Z80_illeg_xDCB_2A, Z80_illeg_xDCB_2B, Z80_illeg_xDCB_2C, Z80_illeg_xDCB_2D, Z80_instr_xDCB_2E, Z80_illeg_xDCB_2F
|
||||
|
||||
!word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB
|
||||
!word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_3E, Z80_illegal__xDCB
|
||||
!word Z80_illeg_xDCB_30, Z80_illeg_xDCB_31, Z80_illeg_xDCB_32, Z80_illeg_xDCB_33, Z80_illeg_xDCB_34, Z80_illeg_xDCB_35, Z80_illeg_xDCB_36, Z80_illeg_xDCB_37
|
||||
!word Z80_illeg_xDCB_38, Z80_illeg_xDCB_39, Z80_illeg_xDCB_3A, Z80_illeg_xDCB_3B, Z80_illeg_xDCB_3C, Z80_illeg_xDCB_3D, Z80_instr_xDCB_3E, Z80_illeg_xDCB_3F
|
||||
|
||||
!word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_46, Z80_illegal__xDCB
|
||||
!word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_4E, Z80_illegal__xDCB
|
||||
!word Z80_illeg_xDCB_40, Z80_illeg_xDCB_41, Z80_illeg_xDCB_42, Z80_illeg_xDCB_43, Z80_illeg_xDCB_44, Z80_illeg_xDCB_45, Z80_instr_xDCB_46, Z80_illeg_xDCB_47
|
||||
!word Z80_illeg_xDCB_48, Z80_illeg_xDCB_49, Z80_illeg_xDCB_4A, Z80_illeg_xDCB_4B, Z80_illeg_xDCB_4C, Z80_illeg_xDCB_4D, Z80_instr_xDCB_4E, Z80_illeg_xDCB_4F
|
||||
|
||||
!word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_56, Z80_illegal__xDCB
|
||||
!word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_5E, Z80_illegal__xDCB
|
||||
!word Z80_illeg_xDCB_50, Z80_illeg_xDCB_51, Z80_illeg_xDCB_52, Z80_illeg_xDCB_53, Z80_illeg_xDCB_54, Z80_illeg_xDCB_55, Z80_instr_xDCB_56, Z80_illeg_xDCB_57
|
||||
!word Z80_illeg_xDCB_58, Z80_illeg_xDCB_59, Z80_illeg_xDCB_5A, Z80_illeg_xDCB_5B, Z80_illeg_xDCB_5C, Z80_illeg_xDCB_5D, Z80_instr_xDCB_5E, Z80_illeg_xDCB_5F
|
||||
|
||||
!word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_66, Z80_illegal__xDCB
|
||||
!word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_6E, Z80_illegal__xDCB
|
||||
!word Z80_illeg_xDCB_60, Z80_illeg_xDCB_61, Z80_illeg_xDCB_62, Z80_illeg_xDCB_63, Z80_illeg_xDCB_64, Z80_illeg_xDCB_65, Z80_instr_xDCB_66, Z80_illeg_xDCB_67
|
||||
!word Z80_illeg_xDCB_68, Z80_illeg_xDCB_69, Z80_illeg_xDCB_6A, Z80_illeg_xDCB_6B, Z80_illeg_xDCB_6C, Z80_illeg_xDCB_6D, Z80_instr_xDCB_6E, Z80_illeg_xDCB_6F
|
||||
|
||||
!word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_76, Z80_illegal__xDCB
|
||||
!word Z80_illeg_xDCB_70, Z80_illeg_xDCB_71, Z80_illeg_xDCB_72, Z80_illeg_xDCB_73, Z80_illeg_xDCB_74, Z80_illeg_xDCB_75, Z80_instr_xDCB_76, Z80_illeg_xDCB_77
|
||||
!word Z80_illeg_xDCB_78, Z80_illeg_xDCB_79, Z80_illeg_xDCB_7A, Z80_illeg_xDCB_7B, Z80_illeg_xDCB_7C, Z80_illeg_xDCB_7D, Z80_instr_xDCB_7E, Z80_illeg_xDCB_7F
|
||||
|
||||
Z80_vectab_xDCB_1:
|
||||
|
||||
!word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_86, Z80_illegal__xDCB
|
||||
!word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_8E, Z80_illegal__xDCB
|
||||
!word Z80_illeg_xDCB_80, Z80_illeg_xDCB_81, Z80_illeg_xDCB_82, Z80_illeg_xDCB_83, Z80_illeg_xDCB_84, Z80_illeg_xDCB_85, Z80_instr_xDCB_86, Z80_illeg_xDCB_87
|
||||
!word Z80_illeg_xDCB_88, Z80_illeg_xDCB_89, Z80_illeg_xDCB_8A, Z80_illeg_xDCB_8B, Z80_illeg_xDCB_8C, Z80_illeg_xDCB_8D, Z80_instr_xDCB_8E, Z80_illeg_xDCB_8F
|
||||
|
||||
!word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_96, Z80_illegal__xDCB
|
||||
!word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_9E, Z80_illegal__xDCB
|
||||
!word Z80_illeg_xDCB_90, Z80_illeg_xDCB_91, Z80_illeg_xDCB_92, Z80_illeg_xDCB_93, Z80_illeg_xDCB_94, Z80_illeg_xDCB_95, Z80_instr_xDCB_96, Z80_illeg_xDCB_97
|
||||
!word Z80_illeg_xDCB_98, Z80_illeg_xDCB_99, Z80_illeg_xDCB_9A, Z80_illeg_xDCB_9B, Z80_illeg_xDCB_9C, Z80_illeg_xDCB_9D, Z80_instr_xDCB_9E, Z80_illeg_xDCB_9F
|
||||
|
||||
!word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_A6, Z80_illegal__xDCB
|
||||
!word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_AE, Z80_illegal__xDCB
|
||||
!word Z80_illeg_xDCB_A0, Z80_illeg_xDCB_A1, Z80_illeg_xDCB_A2, Z80_illeg_xDCB_A3, Z80_illeg_xDCB_A4, Z80_illeg_xDCB_A5, Z80_instr_xDCB_A6, Z80_illeg_xDCB_A7
|
||||
!word Z80_illeg_xDCB_A8, Z80_illeg_xDCB_A9, Z80_illeg_xDCB_AA, Z80_illeg_xDCB_AB, Z80_illeg_xDCB_AC, Z80_illeg_xDCB_AD, Z80_instr_xDCB_AE, Z80_illeg_xDCB_AF
|
||||
|
||||
!word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_B6, Z80_illegal__xDCB
|
||||
!word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_BE, Z80_illegal__xDCB
|
||||
!word Z80_illeg_xDCB_B0, Z80_illeg_xDCB_B1, Z80_illeg_xDCB_B2, Z80_illeg_xDCB_B3, Z80_illeg_xDCB_B4, Z80_illeg_xDCB_B5, Z80_instr_xDCB_B6, Z80_illeg_xDCB_B7
|
||||
!word Z80_illeg_xDCB_B8, Z80_illeg_xDCB_B9, Z80_illeg_xDCB_BA, Z80_illeg_xDCB_BB, Z80_illeg_xDCB_BC, Z80_illeg_xDCB_BD, Z80_instr_xDCB_BE, Z80_illeg_xDCB_BF
|
||||
|
||||
!word Z80_illeg_xDCB_C0, Z80_illeg_xDCB_C1, Z80_illeg_xDCB_C2, Z80_illeg_xDCB_C3, Z80_illeg_xDCB_C4, Z80_illeg_xDCB_C5, Z80_instr_xDCB_C6, Z80_illeg_xDCB_C7
|
||||
!word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_CE, Z80_illegal__xDCB
|
||||
!word Z80_illeg_xDCB_C8, Z80_illeg_xDCB_C9, Z80_illeg_xDCB_CA, Z80_illeg_xDCB_CB, Z80_illeg_xDCB_CC, Z80_illeg_xDCB_CD, Z80_instr_xDCB_CE, Z80_illeg_xDCB_CF
|
||||
|
||||
!word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_D6, Z80_illegal__xDCB
|
||||
!word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_DE, Z80_illegal__xDCB
|
||||
!word Z80_illeg_xDCB_D0, Z80_illeg_xDCB_D1, Z80_illeg_xDCB_D2, Z80_illeg_xDCB_D3, Z80_illeg_xDCB_D4, Z80_illeg_xDCB_D5, Z80_instr_xDCB_D6, Z80_illeg_xDCB_D7
|
||||
!word Z80_illeg_xDCB_D8, Z80_illeg_xDCB_D9, Z80_illeg_xDCB_DA, Z80_illeg_xDCB_DB, Z80_illeg_xDCB_DC, Z80_illeg_xDCB_DD, Z80_instr_xDCB_DE, Z80_illeg_xDCB_DF
|
||||
|
||||
!word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_E6, Z80_illegal__xDCB
|
||||
!word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_EE, Z80_illegal__xDCB
|
||||
!word Z80_illeg_xDCB_E0, Z80_illeg_xDCB_E1, Z80_illeg_xDCB_E2, Z80_illeg_xDCB_E3, Z80_illeg_xDCB_E4, Z80_illeg_xDCB_E5, Z80_instr_xDCB_E6, Z80_illeg_xDCB_E7
|
||||
!word Z80_illeg_xDCB_E8, Z80_illeg_xDCB_E9, Z80_illeg_xDCB_EA, Z80_illeg_xDCB_EB, Z80_illeg_xDCB_EC, Z80_illeg_xDCB_ED, Z80_instr_xDCB_EE, Z80_illeg_xDCB_EF
|
||||
|
||||
!word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_F6, Z80_illegal__xDCB
|
||||
!word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_FE, Z80_illegal__xDCB
|
||||
!word Z80_illeg_xDCB_F0, Z80_illeg_xDCB_F1, Z80_illeg_xDCB_F2, Z80_illeg_xDCB_F3, Z80_illeg_xDCB_F4, Z80_illeg_xDCB_F5, Z80_instr_xDCB_F6, Z80_illeg_xDCB_F7
|
||||
!word Z80_illeg_xDCB_F8, Z80_illeg_xDCB_F9, Z80_illeg_xDCB_FA, Z80_illeg_xDCB_FB, Z80_illeg_xDCB_FC, Z80_illeg_xDCB_FD, Z80_instr_xDCB_FE, Z80_illeg_xDCB_FF
|
||||
@@ -440,49 +440,98 @@ Z80_common_bitHL_1:
|
||||
|
||||
; bits taken from index register + displacement
|
||||
|
||||
Z80_illeg_xDCB_40: ; BIT 0,(IXY+d)
|
||||
Z80_illeg_xDCB_41: ; BIT 0,(IXY+d)
|
||||
Z80_illeg_xDCB_42: ; BIT 0,(IXY+d)
|
||||
Z80_illeg_xDCB_43: ; BIT 0,(IXY+d)
|
||||
Z80_illeg_xDCB_44: ; BIT 0,(IXY+d)
|
||||
Z80_illeg_xDCB_45: ; BIT 0,(IXY+d)
|
||||
Z80_instr_xDCB_46: ; BIT 0,(IXY+d)
|
||||
Z80_illeg_xDCB_47: ; BIT 0,(IXY+d)
|
||||
|
||||
lda [PTR_IXY_d],z
|
||||
and #%00000001
|
||||
bne Z80_common_bitIXYx_1
|
||||
bra Z80_common_bitIXYx_0
|
||||
|
||||
Z80_illeg_xDCB_48: ; BIT 1,(IXY+d)
|
||||
Z80_illeg_xDCB_49: ; BIT 1,(IXY+d)
|
||||
Z80_illeg_xDCB_4A: ; BIT 1,(IXY+d)
|
||||
Z80_illeg_xDCB_4B: ; BIT 1,(IXY+d)
|
||||
Z80_illeg_xDCB_4C: ; BIT 1,(IXY+d)
|
||||
Z80_illeg_xDCB_4D: ; BIT 1,(IXY+d)
|
||||
Z80_instr_xDCB_4E: ; BIT 1,(IXY+d)
|
||||
Z80_illeg_xDCB_4F: ; BIT 1,(IXY+d)
|
||||
|
||||
lda [PTR_IXY_d],z
|
||||
and #%00000010
|
||||
bne Z80_common_bitIXYx_1
|
||||
bra Z80_common_bitIXYx_0
|
||||
|
||||
Z80_illeg_xDCB_50: ; BIT 2,(IXY+d)
|
||||
Z80_illeg_xDCB_51: ; BIT 2,(IXY+d)
|
||||
Z80_illeg_xDCB_52: ; BIT 2,(IXY+d)
|
||||
Z80_illeg_xDCB_53: ; BIT 2,(IXY+d)
|
||||
Z80_illeg_xDCB_54: ; BIT 2,(IXY+d)
|
||||
Z80_illeg_xDCB_55: ; BIT 2,(IXY+d)
|
||||
Z80_instr_xDCB_56: ; BIT 2,(IXY+d)
|
||||
Z80_illeg_xDCB_57: ; BIT 2,(IXY+d)
|
||||
|
||||
lda [PTR_IXY_d],z
|
||||
and #%00000100
|
||||
bne Z80_common_bitIXYx_1
|
||||
bra Z80_common_bitIXYx_0
|
||||
|
||||
Z80_illeg_xDCB_58: ; BIT 3,(IXY+d)
|
||||
Z80_illeg_xDCB_59: ; BIT 3,(IXY+d)
|
||||
Z80_illeg_xDCB_5A: ; BIT 3,(IXY+d)
|
||||
Z80_illeg_xDCB_5B: ; BIT 3,(IXY+d)
|
||||
Z80_illeg_xDCB_5C: ; BIT 3,(IXY+d)
|
||||
Z80_illeg_xDCB_5D: ; BIT 3,(IXY+d)
|
||||
Z80_instr_xDCB_5E: ; BIT 3,(IXY+d)
|
||||
Z80_illeg_xDCB_5F: ; BIT 3,(IXY+d)
|
||||
|
||||
lda [PTR_IXY_d],z
|
||||
and #%00001000
|
||||
bne Z80_common_bitIXYx_1
|
||||
bra Z80_common_bitIXYx_0
|
||||
|
||||
Z80_illeg_xDCB_60: ; BIT 4,(IXY+d)
|
||||
Z80_illeg_xDCB_61: ; BIT 4,(IXY+d)
|
||||
Z80_illeg_xDCB_62: ; BIT 4,(IXY+d)
|
||||
Z80_illeg_xDCB_63: ; BIT 4,(IXY+d)
|
||||
Z80_illeg_xDCB_64: ; BIT 4,(IXY+d)
|
||||
Z80_illeg_xDCB_65: ; BIT 4,(IXY+d)
|
||||
Z80_instr_xDCB_66: ; BIT 4,(IXY+d)
|
||||
Z80_illeg_xDCB_67: ; BIT 4,(IXY+d)
|
||||
|
||||
lda [PTR_IXY_d],z
|
||||
and #%00010000
|
||||
bne Z80_common_bitIXYx_1
|
||||
bra Z80_common_bitIXYx_0
|
||||
|
||||
Z80_illeg_xDCB_68: ; BIT 5,(IXY+d)
|
||||
Z80_illeg_xDCB_69: ; BIT 5,(IXY+d)
|
||||
Z80_illeg_xDCB_6A: ; BIT 5,(IXY+d)
|
||||
Z80_illeg_xDCB_6B: ; BIT 5,(IXY+d)
|
||||
Z80_illeg_xDCB_6C: ; BIT 5,(IXY+d)
|
||||
Z80_illeg_xDCB_6D: ; BIT 5,(IXY+d)
|
||||
Z80_instr_xDCB_6E: ; BIT 5,(IXY+d)
|
||||
Z80_illeg_xDCB_6F: ; BIT 5,(IXY+d)
|
||||
|
||||
lda [PTR_IXY_d],z
|
||||
and #%00100000
|
||||
bne Z80_common_bitIXYx_1
|
||||
bra Z80_common_bitIXYx_0
|
||||
|
||||
Z80_illeg_xDCB_70: ; BIT 6,(IXY+d)
|
||||
Z80_illeg_xDCB_71: ; BIT 6,(IXY+d)
|
||||
Z80_illeg_xDCB_72: ; BIT 6,(IXY+d)
|
||||
Z80_illeg_xDCB_73: ; BIT 6,(IXY+d)
|
||||
Z80_illeg_xDCB_74: ; BIT 6,(IXY+d)
|
||||
Z80_illeg_xDCB_75: ; BIT 6,(IXY+d)
|
||||
Z80_instr_xDCB_76: ; BIT 6,(IXY+d)
|
||||
Z80_illeg_xDCB_77: ; BIT 6,(IXY+d)
|
||||
|
||||
lda [PTR_IXY_d],z
|
||||
and #%01000000
|
||||
|
||||
@@ -0,0 +1,5 @@
|
||||
|
||||
;
|
||||
; Z80 bit set/reset/test instructions - these illegals are size optimized
|
||||
;
|
||||
|
||||
@@ -2,3 +2,161 @@
|
||||
;
|
||||
; Z80 call/return instructions
|
||||
;
|
||||
|
||||
|
||||
Z80_instr_CD: ; CALL nn
|
||||
|
||||
jsr (VEC_fetch_value)
|
||||
pha
|
||||
jsr (VEC_fetch_value)
|
||||
pha
|
||||
|
||||
lda REG_PC+1
|
||||
jsr (VEC_store_stack)
|
||||
lda REG_PC+0
|
||||
jsr (VEC_store_stack)
|
||||
|
||||
pla
|
||||
sta REG_PC+1
|
||||
pla
|
||||
sta REG_PC+0
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_C4: ; CALL NZ,nn
|
||||
|
||||
bbr6 REG_F,Z80_instr_CD
|
||||
inw REG_PC
|
||||
inw REG_PC
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_CC: ; CALL Z,nn
|
||||
|
||||
bbs6 REG_F,Z80_instr_CD
|
||||
inw REG_PC
|
||||
inw REG_PC
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_D4: ; CALL NC,nn
|
||||
|
||||
bbr0 REG_F,Z80_instr_CD
|
||||
inw REG_PC
|
||||
inw REG_PC
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_DC: ; CALL C,nn
|
||||
|
||||
bbs0 REG_F,Z80_instr_CD
|
||||
inw REG_PC
|
||||
inw REG_PC
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_E4: ; CALL PO,nn
|
||||
|
||||
bbr2 REG_F,Z80_instr_CD
|
||||
inw REG_PC
|
||||
inw REG_PC
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_EC: ; CALL PE,nn
|
||||
|
||||
bbs2 REG_F,Z80_instr_CD
|
||||
inw REG_PC
|
||||
inw REG_PC
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_F4: ; CALL P,nn
|
||||
|
||||
bbr7 REG_F,Z80_instr_CD
|
||||
inw REG_PC
|
||||
inw REG_PC
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_FC: ; CALL M,nn
|
||||
|
||||
bbs7 REG_F,Z80_instr_CD
|
||||
inw REG_PC
|
||||
inw REG_PC
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_ED_45: ; RETN
|
||||
Z80_illeg_ED_55: ; RETN
|
||||
Z80_illeg_ED_5D: ; RETN
|
||||
Z80_illeg_ED_65: ; RETN
|
||||
Z80_illeg_ED_6D: ; RETN
|
||||
Z80_illeg_ED_75: ; RETN
|
||||
Z80_illeg_ED_7D: ; RETN
|
||||
|
||||
lda REG_IFF2
|
||||
sta REG_IFF1
|
||||
|
||||
Z80_instr_ED_4D: ; RETTI
|
||||
Z80_instr_C9: ; RET
|
||||
|
||||
jsr (VEC_fetch_stack)
|
||||
sta REG_PC+0
|
||||
jsr (VEC_fetch_stack)
|
||||
sta REG_PC+1
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_C0: ; RET NZ
|
||||
|
||||
bbr6 REG_F,Z80_instr_C9
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_C8: ; RET Z
|
||||
|
||||
bbs6 REG_F,Z80_instr_C9
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_D0: ; RET NC
|
||||
|
||||
bbr0 REG_F,Z80_instr_C9
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_D8: ; RET C
|
||||
|
||||
bbs0 REG_F,Z80_instr_C9
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_E0: ; RET PO
|
||||
|
||||
bbr2 REG_F,Z80_instr_C9
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_E8: ; RET PE
|
||||
|
||||
bbs2 REG_F,Z80_instr_C9
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_F0: ; RET P
|
||||
|
||||
bbr7 REG_F,Z80_instr_C9
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_F8: ; RET M
|
||||
|
||||
bbs7 REG_F,Z80_instr_C9
|
||||
jmp ZVM_next
|
||||
|
||||
|
||||
!macro Z80_RST .P {
|
||||
|
||||
lda REG_PC+1
|
||||
jsr (VEC_store_stack)
|
||||
lda REG_PC+0
|
||||
jsr (VEC_store_stack)
|
||||
lda #$00
|
||||
sta REG_PC+1
|
||||
lda #.P
|
||||
sta REG_PC+0
|
||||
jmp ZVM_next
|
||||
}
|
||||
|
||||
Z80_instr_C7: +Z80_RST $00 ; RST 00H
|
||||
Z80_instr_CF: +Z80_RST $08 ; RST 08H
|
||||
Z80_instr_D7: +Z80_RST $10 ; RST 10H
|
||||
Z80_instr_DF: +Z80_RST $18 ; RST 18H
|
||||
Z80_instr_E7: +Z80_RST $20 ; RST 20H
|
||||
Z80_instr_EF: +Z80_RST $28 ; RST 28H
|
||||
Z80_instr_F7: +Z80_RST $30 ; RST 30H
|
||||
Z80_instr_FF: +Z80_RST $38 ; RST 38H
|
||||
+168
-131
@@ -59,153 +59,194 @@ Z80_instr_7B: +Z80_LD_REGn_REGn REG_A, REG_E ;
|
||||
Z80_instr_7C: +Z80_LD_REGn_REGn REG_A, REG_H ; LD A,H
|
||||
Z80_instr_7D: +Z80_LD_REGn_REGn REG_A, REG_L ; LD A,L
|
||||
|
||||
;
|
||||
; load register with immediate value
|
||||
;
|
||||
Z80_illeg_DD_44: +Z80_LD_REGn_REGn REG_B, REG_IXH ; LD B,IXH
|
||||
Z80_illeg_DD_45: +Z80_LD_REGn_REGn REG_B, REG_IXL ; LD B,IXL
|
||||
Z80_illeg_DD_4C: +Z80_LD_REGn_REGn REG_C, REG_IXH ; LD C,IXH
|
||||
Z80_illeg_DD_4D: +Z80_LD_REGn_REGn REG_C, REG_IXL ; LD C,IXL
|
||||
Z80_illeg_DD_54: +Z80_LD_REGn_REGn REG_D, REG_IXH ; LD D,IXH
|
||||
Z80_illeg_DD_55: +Z80_LD_REGn_REGn REG_D, REG_IXL ; LD D,IXL
|
||||
Z80_illeg_DD_5C: +Z80_LD_REGn_REGn REG_E, REG_IXH ; LD E,IXH
|
||||
Z80_illeg_DD_5D: +Z80_LD_REGn_REGn REG_E, REG_IXL ; LD E,IXL
|
||||
Z80_illeg_DD_7C: +Z80_LD_REGn_REGn REG_A, REG_IXH ; LD A,IXH
|
||||
Z80_illeg_DD_7D: +Z80_LD_REGn_REGn REG_A, REG_IXL ; LD A,IXL
|
||||
|
||||
Z80_instr_06: ; LD B,n
|
||||
Z80_illeg_FD_44: +Z80_LD_REGn_REGn REG_B, REG_IYH ; LD B,IYH
|
||||
Z80_illeg_FD_45: +Z80_LD_REGn_REGn REG_B, REG_IYL ; LD B,IYL
|
||||
Z80_illeg_FD_4C: +Z80_LD_REGn_REGn REG_C, REG_IYH ; LD C,IYH
|
||||
Z80_illeg_FD_4D: +Z80_LD_REGn_REGn REG_C, REG_IYL ; LD C,IYL
|
||||
Z80_illeg_FD_54: +Z80_LD_REGn_REGn REG_D, REG_IYH ; LD D,IYH
|
||||
Z80_illeg_FD_55: +Z80_LD_REGn_REGn REG_D, REG_IYL ; LD D,IYL
|
||||
Z80_illeg_FD_5C: +Z80_LD_REGn_REGn REG_E, REG_IYH ; LD E,IYH
|
||||
Z80_illeg_FD_5D: +Z80_LD_REGn_REGn REG_E, REG_IYL ; LD E,IYL
|
||||
Z80_illeg_FD_7C: +Z80_LD_REGn_REGn REG_A, REG_IYH ; LD A,IYH
|
||||
Z80_illeg_FD_7D: +Z80_LD_REGn_REGn REG_A, REG_IYL ; LD A,IYL
|
||||
|
||||
Z80_illeg_DD_60: +Z80_LD_REGn_REGn REG_IXH, REG_B ; LD IXH,B
|
||||
Z80_illeg_DD_61: +Z80_LD_REGn_REGn REG_IXH, REG_C ; LD IXH,C
|
||||
Z80_illeg_DD_62: +Z80_LD_REGn_REGn REG_IXH, REG_D ; LD IXH,D
|
||||
Z80_illeg_DD_63: +Z80_LD_REGn_REGn REG_IXH, REG_E ; LD IXH,E
|
||||
Z80_illeg_DD_65: +Z80_LD_REGn_REGn REG_IXH, REG_IXL ; LD IXH,IXL
|
||||
Z80_illeg_DD_67: +Z80_LD_REGn_REGn REG_IXH, REG_A ; LD IXH,A
|
||||
|
||||
Z80_illeg_DD_68: +Z80_LD_REGn_REGn REG_IXL, REG_B ; LD IXL,B
|
||||
Z80_illeg_DD_69: +Z80_LD_REGn_REGn REG_IXL, REG_C ; LD IXL,C
|
||||
Z80_illeg_DD_6A: +Z80_LD_REGn_REGn REG_IXL, REG_D ; LD IXL,D
|
||||
Z80_illeg_DD_6B: +Z80_LD_REGn_REGn REG_IXL, REG_E ; LD IXL,E
|
||||
Z80_illeg_DD_6C: +Z80_LD_REGn_REGn REG_IXL, REG_IXH ; LD IXL,IXH
|
||||
Z80_illeg_DD_6F: +Z80_LD_REGn_REGn REG_IXL, REG_A ; LD IXL,A
|
||||
|
||||
Z80_illeg_FD_60: +Z80_LD_REGn_REGn REG_IYH, REG_B ; LD IYH,B
|
||||
Z80_illeg_FD_61: +Z80_LD_REGn_REGn REG_IYH, REG_C ; LD IYH,C
|
||||
Z80_illeg_FD_62: +Z80_LD_REGn_REGn REG_IYH, REG_D ; LD IYH,D
|
||||
Z80_illeg_FD_63: +Z80_LD_REGn_REGn REG_IYH, REG_E ; LD IYH,E
|
||||
Z80_illeg_FD_65: +Z80_LD_REGn_REGn REG_IYH, REG_IYL ; LD IYH,IYL
|
||||
Z80_illeg_FD_67: +Z80_LD_REGn_REGn REG_IYH, REG_A ; LD IYH,A
|
||||
|
||||
Z80_illeg_FD_68: +Z80_LD_REGn_REGn REG_IYL, REG_B ; LD IYL,B
|
||||
Z80_illeg_FD_69: +Z80_LD_REGn_REGn REG_IYL, REG_C ; LD IYL,C
|
||||
Z80_illeg_FD_6A: +Z80_LD_REGn_REGn REG_IYL, REG_D ; LD IYL,D
|
||||
Z80_illeg_FD_6B: +Z80_LD_REGn_REGn REG_IYL, REG_E ; LD IYL,E
|
||||
Z80_illeg_FD_6C: +Z80_LD_REGn_REGn REG_IYL, REG_IYH ; LD IYL,IYH
|
||||
Z80_illeg_FD_6F: +Z80_LD_REGn_REGn REG_IYL, REG_A ; LD IYL,A
|
||||
|
||||
!macro Z80_LD_REGn_n .REGn {
|
||||
jsr (VEC_fetch_value)
|
||||
sta REG_B
|
||||
sta .REGn
|
||||
jmp ZVM_next
|
||||
}
|
||||
|
||||
Z80_instr_0E: ; LD C,n
|
||||
Z80_instr_06: +Z80_LD_REGn_n REG_B ; LD B,n
|
||||
Z80_instr_0E: +Z80_LD_REGn_n REG_C ; LD C,n
|
||||
Z80_instr_16: +Z80_LD_REGn_n REG_D ; LD D,n
|
||||
Z80_instr_1E: +Z80_LD_REGn_n REG_E ; LD E,n
|
||||
Z80_instr_26: +Z80_LD_REGn_n REG_H ; LD H,n
|
||||
Z80_instr_2E: +Z80_LD_REGn_n REG_L ; LD L,n
|
||||
Z80_instr_3E: +Z80_LD_REGn_n REG_A ; LD A,n
|
||||
|
||||
jsr (VEC_fetch_value)
|
||||
sta REG_C
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_16: ; LD D,n
|
||||
|
||||
jsr (VEC_fetch_value)
|
||||
sta REG_D
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_1E: ; LD E,n
|
||||
|
||||
jsr (VEC_fetch_value)
|
||||
sta REG_E
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_26: ; LD H,n
|
||||
|
||||
jsr (VEC_fetch_value)
|
||||
sta REG_H
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_2E: ; LD L,n
|
||||
|
||||
jsr (VEC_fetch_value)
|
||||
sta REG_L
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_3E: ; LD A,n
|
||||
|
||||
jsr (VEC_fetch_value)
|
||||
sta REG_A
|
||||
jmp ZVM_next
|
||||
|
||||
;
|
||||
; load register with memory content (via HL)
|
||||
;
|
||||
|
||||
Z80_instr_46: ; LD B,(HL)
|
||||
Z80_illeg_DD_26: +Z80_LD_REGn_n REG_IXH ; LD IXH,n
|
||||
Z80_illeg_DD_2E: +Z80_LD_REGn_n REG_IXL ; LD IXL,n
|
||||
Z80_illeg_FD_26: +Z80_LD_REGn_n REG_IYH ; LD IYH,n
|
||||
Z80_illeg_FD_2E: +Z80_LD_REGn_n REG_IYL ; LD IYL,n
|
||||
|
||||
!macro Z80_LD_REGn_VIA_HL .REGn {
|
||||
jsr (VEC_fetch_via_HL)
|
||||
sta REG_B
|
||||
sta .REGn
|
||||
jmp ZVM_next
|
||||
}
|
||||
|
||||
Z80_instr_4E: ; LD C,(HL)
|
||||
Z80_instr_46: +Z80_LD_REGn_VIA_HL REG_B ; LD B,(HL)
|
||||
Z80_instr_4E: +Z80_LD_REGn_VIA_HL REG_C ; LD C,(HL)
|
||||
Z80_instr_56: +Z80_LD_REGn_VIA_HL REG_D ; LD D,(HL)
|
||||
Z80_instr_5E: +Z80_LD_REGn_VIA_HL REG_E ; LD E,(HL)
|
||||
Z80_instr_66: +Z80_LD_REGn_VIA_HL REG_H ; LD H,(HL)
|
||||
Z80_instr_6E: +Z80_LD_REGn_VIA_HL REG_L ; LD L,(HL)
|
||||
Z80_instr_7E: +Z80_LD_REGn_VIA_HL REG_A ; LD A,(HL)
|
||||
|
||||
jsr (VEC_fetch_via_HL)
|
||||
sta REG_C
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_56: ; LD D,(HL)
|
||||
|
||||
jsr (VEC_fetch_via_HL)
|
||||
sta REG_D
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_5E: ; LD E,(HL)
|
||||
|
||||
jsr (VEC_fetch_via_HL)
|
||||
sta REG_E
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_66: ; LD H,(HL)
|
||||
|
||||
jsr (VEC_fetch_via_HL)
|
||||
sta REG_H
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_6E: ; LD L,(HL)
|
||||
|
||||
jsr (VEC_fetch_via_HL)
|
||||
sta REG_L
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_7E: ; LD A,(HL)
|
||||
|
||||
jsr (VEC_fetch_via_HL)
|
||||
sta REG_A
|
||||
jmp ZVM_next
|
||||
|
||||
; XXX put here LD r,(IX+d) family
|
||||
; XXX put here LD r,(IY+d) family
|
||||
|
||||
;
|
||||
; load memory content (via HL) with register
|
||||
;
|
||||
|
||||
Z80_instr_70: ; LD (HL),B
|
||||
|
||||
lda REG_B
|
||||
!macro Z80_LD_VIA_HL_REGn .REGn {
|
||||
lda .REGn
|
||||
jsr (VEC_store_via_HL)
|
||||
jmp ZVM_next
|
||||
}
|
||||
|
||||
Z80_instr_71: ; LD (HL),C
|
||||
Z80_instr_70: +Z80_LD_VIA_HL_REGn REG_B ; LD (HL),B
|
||||
Z80_instr_71: +Z80_LD_VIA_HL_REGn REG_C ; LD (HL),C
|
||||
Z80_instr_72: +Z80_LD_VIA_HL_REGn REG_D ; LD (HL),D
|
||||
Z80_instr_73: +Z80_LD_VIA_HL_REGn REG_E ; LD (HL),E
|
||||
Z80_instr_74: +Z80_LD_VIA_HL_REGn REG_H ; LD (HL),H
|
||||
Z80_instr_75: +Z80_LD_VIA_HL_REGn REG_L ; LD (HL),L
|
||||
Z80_instr_77: +Z80_LD_VIA_HL_REGn REG_A ; LD (HL),A
|
||||
|
||||
lda REG_C
|
||||
jsr (VEC_store_via_HL)
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_72: ; LD (HL),D
|
||||
|
||||
lda REG_D
|
||||
jsr (VEC_store_via_HL)
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_73: ; LD (HL),E
|
||||
|
||||
lda REG_E
|
||||
jsr (VEC_store_via_HL)
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_74: ; LD (HL),H
|
||||
|
||||
lda REG_H
|
||||
jsr (VEC_store_via_HL)
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_75: ; LD (HL),L
|
||||
|
||||
lda REG_L
|
||||
jsr (VEC_store_via_HL)
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_77: ; LD (HL),A
|
||||
Z80_instr_02: ; LD (BC),A
|
||||
|
||||
lda REG_A
|
||||
jsr (VEC_store_via_HL)
|
||||
jsr (VEC_store_via_BC)
|
||||
jmp ZVM_next
|
||||
|
||||
; XXX put here LD (IX+d),r family
|
||||
; XXX put here LD (IY+d),r family
|
||||
Z80_instr_0A: ; LD A,(BC)
|
||||
|
||||
;
|
||||
; load memory content (via HL) with immediate value
|
||||
;
|
||||
jsr (VEC_fetch_via_BC)
|
||||
sta REG_A
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_12: ; LD (DE),A
|
||||
|
||||
lda REG_A
|
||||
jsr (VEC_store_via_DE)
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_1A: ; LD A,(DE)
|
||||
|
||||
jsr (VEC_fetch_via_DE)
|
||||
sta REG_A
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_32: ; LD (nn),A
|
||||
|
||||
lda REG_A
|
||||
jsr (VEC_store_via_nn)
|
||||
jmp ZVM_next
|
||||
|
||||
Z80_instr_3A: ; LD A,(nn)
|
||||
|
||||
jsr (VEC_fetch_via_nn)
|
||||
sta REG_A
|
||||
jmp ZVM_next
|
||||
|
||||
!macro Z80_LD_REGn_VIA_IX_d .REGn {
|
||||
jsr (VEC_fetch_via_IX_d)
|
||||
sta .REGn
|
||||
jmp ZVM_next
|
||||
}
|
||||
|
||||
Z80_instr_DD_46: +Z80_LD_REGn_VIA_IX_d REG_B ; LD B,(IX+d)
|
||||
Z80_instr_DD_4E: +Z80_LD_REGn_VIA_IX_d REG_C ; LD C,(IX+d)
|
||||
Z80_instr_DD_56: +Z80_LD_REGn_VIA_IX_d REG_D ; LD D,(IX+d)
|
||||
Z80_instr_DD_5E: +Z80_LD_REGn_VIA_IX_d REG_E ; LD E,(IX+d)
|
||||
Z80_instr_DD_66: +Z80_LD_REGn_VIA_IX_d REG_H ; LD H,(IX+d)
|
||||
Z80_instr_DD_6E: +Z80_LD_REGn_VIA_IX_d REG_L ; LD L,(IX+d)
|
||||
Z80_instr_DD_7E: +Z80_LD_REGn_VIA_IX_d REG_A ; LD A,(IX+d)
|
||||
|
||||
!macro Z80_LD_REGn_VIA_IY_d .REGn {
|
||||
jsr (VEC_fetch_via_IY_d)
|
||||
sta .REGn
|
||||
jmp ZVM_next
|
||||
}
|
||||
|
||||
Z80_instr_FD_46: +Z80_LD_REGn_VIA_IY_d REG_B ; LD B,(IY+d)
|
||||
Z80_instr_FD_4E: +Z80_LD_REGn_VIA_IY_d REG_C ; LD C,(IY+d)
|
||||
Z80_instr_FD_56: +Z80_LD_REGn_VIA_IY_d REG_D ; LD D,(IY+d)
|
||||
Z80_instr_FD_5E: +Z80_LD_REGn_VIA_IY_d REG_E ; LD E,(IY+d)
|
||||
Z80_instr_FD_66: +Z80_LD_REGn_VIA_IY_d REG_H ; LD H,(IY+d)
|
||||
Z80_instr_FD_6E: +Z80_LD_REGn_VIA_IY_d REG_L ; LD L,(IY+d)
|
||||
Z80_instr_FD_7E: +Z80_LD_REGn_VIA_IY_d REG_A ; LD A,(IY+d)
|
||||
|
||||
!macro Z80_LD_VIA_IX_d_REG_n .REGn {
|
||||
lda .REGn
|
||||
jsr (VEC_store_via_IX_d)
|
||||
jmp ZVM_next
|
||||
}
|
||||
|
||||
Z80_instr_DD_70: +Z80_LD_VIA_IX_d_REG_n REG_B ; LD (IX+d),B
|
||||
Z80_instr_DD_71: +Z80_LD_VIA_IX_d_REG_n REG_C ; LD (IX+d),C
|
||||
Z80_instr_DD_72: +Z80_LD_VIA_IX_d_REG_n REG_D ; LD (IX+d),D
|
||||
Z80_instr_DD_73: +Z80_LD_VIA_IX_d_REG_n REG_E ; LD (IX+d),E
|
||||
Z80_instr_DD_74: +Z80_LD_VIA_IX_d_REG_n REG_H ; LD (IX+d),H
|
||||
Z80_instr_DD_75: +Z80_LD_VIA_IX_d_REG_n REG_L ; LD (IX+d),L
|
||||
Z80_instr_DD_77: +Z80_LD_VIA_IX_d_REG_n REG_A ; LD (IX+d),A
|
||||
|
||||
!macro Z80_LD_VIA_IY_d_REG_n .REGn {
|
||||
lda .REGn
|
||||
jsr (VEC_store_via_IY_d)
|
||||
jmp ZVM_next
|
||||
}
|
||||
|
||||
Z80_instr_FD_70: +Z80_LD_VIA_IY_d_REG_n REG_B ; LD (IY+d),B
|
||||
Z80_instr_FD_71: +Z80_LD_VIA_IY_d_REG_n REG_C ; LD (IY+d),C
|
||||
Z80_instr_FD_72: +Z80_LD_VIA_IY_d_REG_n REG_D ; LD (IY+d),D
|
||||
Z80_instr_FD_73: +Z80_LD_VIA_IY_d_REG_n REG_E ; LD (IY+d),E
|
||||
Z80_instr_FD_74: +Z80_LD_VIA_IY_d_REG_n REG_H ; LD (IY+d),H
|
||||
Z80_instr_FD_75: +Z80_LD_VIA_IY_d_REG_n REG_L ; LD (IY+d),L
|
||||
Z80_instr_FD_77: +Z80_LD_VIA_IY_d_REG_n REG_A ; LD (IY+d),A
|
||||
|
||||
Z80_instr_36: ; LD (HL),n
|
||||
|
||||
@@ -213,10 +254,6 @@ Z80_instr_36: ; LD (HL),n
|
||||
jsr (VEC_store_via_HL)
|
||||
jmp ZVM_next
|
||||
|
||||
; XXX put here LD (IX+d),n family
|
||||
; XXX put here LD (IY+d),n family
|
||||
; XXX put here LD A,(BC) / LD A,(DE) / LD A,(nn) / LD (BC), A / LD (DE),A / LD (nn),A
|
||||
|
||||
Z80_instr_ED_57: ; LD A,I
|
||||
|
||||
lda REG_F
|
||||
|
||||
@@ -60,6 +60,10 @@ Z80_instr_A2: +Z80_AND_REGn REG_D ;
|
||||
Z80_instr_A3: +Z80_AND_REGn REG_E ; AND E
|
||||
Z80_instr_A4: +Z80_AND_REGn REG_H ; AND H
|
||||
Z80_instr_A5: +Z80_AND_REGn REG_L ; AND L
|
||||
Z80_illeg_DD_A4: +Z80_AND_REGn REG_IXH ; AND IXH
|
||||
Z80_illeg_DD_A5: +Z80_AND_REGn REG_IXL ; AND IXL
|
||||
Z80_illeg_FD_A4: +Z80_AND_REGn REG_IYH ; AND IYH
|
||||
Z80_illeg_FD_A5: +Z80_AND_REGn REG_IXL ; AND IYL
|
||||
Z80_instr_A6: +Z80_AND_VIA_HL ; AND (HL)
|
||||
Z80_instr_A7: +Z80_AND_SELF ; AND A
|
||||
Z80_instr_E6: +Z80_AND_n ; AND n
|
||||
@@ -118,6 +122,10 @@ Z80_instr_B2: +Z80_OR_REGn REG_D ;
|
||||
Z80_instr_B3: +Z80_OR_REGn REG_E ; OR E
|
||||
Z80_instr_B4: +Z80_OR_REGn REG_H ; OR H
|
||||
Z80_instr_B5: +Z80_OR_REGn REG_L ; OR L
|
||||
Z80_illeg_DD_B4: +Z80_OR_REGn REG_IXH ; OR IXH
|
||||
Z80_illeg_DD_B5: +Z80_OR_REGn REG_IXL ; OR IXL
|
||||
Z80_illeg_FD_B4: +Z80_OR_REGn REG_IYH ; OR IYH
|
||||
Z80_illeg_FD_B5: +Z80_OR_REGn REG_IYL ; OR IYL
|
||||
Z80_instr_B6: +Z80_OR_VIA_HL ; OR (HL)
|
||||
Z80_instr_B7: +Z80_OR_SELF ; OR A
|
||||
Z80_instr_F6: +Z80_OR_n ; OR n
|
||||
@@ -173,51 +181,34 @@ Z80_instr_AA: +Z80_XOR_REGn REG_D ;
|
||||
Z80_instr_AB: +Z80_XOR_REGn REG_E ; XOR E
|
||||
Z80_instr_AC: +Z80_XOR_REGn REG_H ; XOR H
|
||||
Z80_instr_AD: +Z80_XOR_REGn REG_L ; XOR L
|
||||
Z80_illeg_DD_AC: +Z80_XOR_REGn REG_IXH ; XOR IXH
|
||||
Z80_illeg_DD_AD: +Z80_XOR_REGn REG_IXL ; XOR IXL
|
||||
Z80_illeg_FD_AC: +Z80_XOR_REGn REG_IYH ; XOR IYH
|
||||
Z80_illeg_FD_AD: +Z80_XOR_REGn REG_IXL ; XOR IYL
|
||||
Z80_instr_AE: +Z80_XOR_VIA_HL ; XOR (HL)
|
||||
Z80_instr_AF: +Z80_XOR_SELF ; XOR A
|
||||
Z80_instr_EE: +Z80_XOR_n ; XOR n
|
||||
Z80_instr_DD_AE: +Z80_XOR_VIA_IX_d ; XOR (IX+d)
|
||||
Z80_instr_FD_AE: +Z80_XOR_VIA_IY_d ; XOR (IY+d)
|
||||
|
||||
; XXX put CP instructions here
|
||||
|
||||
Z80_instr_04: ; INC B
|
||||
|
||||
ldx REG_B
|
||||
inc REG_B
|
||||
!macro Z80_INC_REG_n .REG_n {
|
||||
ldx .REG_n
|
||||
inc .REG_n
|
||||
bra Z80_common_INC
|
||||
}
|
||||
|
||||
Z80_instr_0C: ; INC C
|
||||
Z80_instr_04: +Z80_INC_REG_n REG_B ; INC B
|
||||
Z80_instr_0C: +Z80_INC_REG_n REG_C ; INC C
|
||||
Z80_instr_14: +Z80_INC_REG_n REG_D ; INC D
|
||||
Z80_instr_1C: +Z80_INC_REG_n REG_E ; INC E
|
||||
Z80_instr_24: +Z80_INC_REG_n REG_H ; INC H
|
||||
Z80_instr_2C: +Z80_INC_REG_n REG_L ; INC L
|
||||
Z80_illeg_DD_24: +Z80_INC_REG_n REG_IXH ; INC IXH
|
||||
Z80_illeg_DD_2C: +Z80_INC_REG_n REG_IXL ; INC IXL
|
||||
Z80_illeg_FD_24: +Z80_INC_REG_n REG_IYH ; INC IYH
|
||||
Z80_illeg_FD_2C: +Z80_INC_REG_n REG_IYL ; INC IYL
|
||||
|
||||
ldx REG_C
|
||||
inc REG_C
|
||||
bra Z80_common_INC
|
||||
|
||||
Z80_instr_14: ; INC D
|
||||
|
||||
ldx REG_D
|
||||
inc REG_D
|
||||
bra Z80_common_INC
|
||||
|
||||
Z80_instr_1C: ; INC E
|
||||
|
||||
ldx REG_E
|
||||
inc REG_E
|
||||
bra Z80_common_INC
|
||||
|
||||
Z80_instr_24: ; INC H
|
||||
|
||||
ldx REG_H
|
||||
inc REG_H
|
||||
bra Z80_common_INC
|
||||
|
||||
Z80_instr_2C: ; INC L
|
||||
|
||||
ldx REG_L
|
||||
inc REG_L
|
||||
bra Z80_common_INC
|
||||
|
||||
Z80_instr_3C: ; INC A
|
||||
Z80_instr_3C: ; INC A
|
||||
|
||||
ldx REG_A
|
||||
inc REG_A
|
||||
@@ -256,43 +247,24 @@ Z80_instr_FD_34: ; INC (IY+d)
|
||||
sta [PTR_DATA],z
|
||||
bra Z80_common_INC
|
||||
|
||||
Z80_instr_05: ; DEC B
|
||||
|
||||
ldx REG_B
|
||||
dec REG_B
|
||||
!macro Z80_DEC_REG_n .REG_n {
|
||||
ldx .REG_n
|
||||
dec .REG_n
|
||||
bra Z80_common_DEC
|
||||
}
|
||||
|
||||
Z80_instr_0D: ; DEC C
|
||||
Z80_instr_05: +Z80_DEC_REG_n REG_B ; DEC B
|
||||
Z80_instr_0D: +Z80_DEC_REG_n REG_C ; DEC C
|
||||
Z80_instr_15: +Z80_DEC_REG_n REG_D ; DEC D
|
||||
Z80_instr_1D: +Z80_DEC_REG_n REG_E ; DEC E
|
||||
Z80_instr_25: +Z80_DEC_REG_n REG_H ; DEC H
|
||||
Z80_instr_2D: +Z80_DEC_REG_n REG_L ; DEC L
|
||||
Z80_illeg_DD_25: +Z80_DEC_REG_n REG_IXH ; DEC IXH
|
||||
Z80_illeg_DD_2D: +Z80_DEC_REG_n REG_IXL ; DEC IXL
|
||||
Z80_illeg_FD_25: +Z80_DEC_REG_n REG_IYH ; DEC IYH
|
||||
Z80_illeg_FD_2D: +Z80_DEC_REG_n REG_IYL ; DEC IYL
|
||||
|
||||
ldx REG_C
|
||||
dec REG_C
|
||||
bra Z80_common_DEC
|
||||
|
||||
Z80_instr_15: ; DEC D
|
||||
|
||||
ldx REG_D
|
||||
dec REG_D
|
||||
bra Z80_common_DEC
|
||||
|
||||
Z80_instr_1D: ; DEC E
|
||||
|
||||
ldx REG_E
|
||||
dec REG_E
|
||||
bra Z80_common_DEC
|
||||
|
||||
Z80_instr_25: ; DEC H
|
||||
|
||||
ldx REG_H
|
||||
dec REG_H
|
||||
bra Z80_common_DEC
|
||||
|
||||
Z80_instr_2D: ; DEC L
|
||||
|
||||
ldx REG_L
|
||||
dec REG_L
|
||||
bra Z80_common_DEC
|
||||
|
||||
Z80_instr_3D: ; DEC A
|
||||
Z80_instr_3D: ; DEC A
|
||||
|
||||
ldx REG_A
|
||||
dec REG_A
|
||||
@@ -330,3 +302,5 @@ Z80_instr_FD_35: ; DEC (IY+d)
|
||||
dec
|
||||
sta [PTR_DATA],z
|
||||
bra Z80_common_DEC
|
||||
|
||||
|
||||
+192
-386
@@ -27,11 +27,8 @@ ZVM_store_next:
|
||||
|
||||
}
|
||||
|
||||
; unimplemented/illegal instructions
|
||||
Z80_illegal__DD:
|
||||
Z80_illegal__ED:
|
||||
Z80_illegal__FD:
|
||||
Z80_illegal__xDCB:
|
||||
; unsupported illegal instructions
|
||||
Z80_unsupported:
|
||||
; XXX add a separate handler for illegal instructions
|
||||
; LD instructions with no effect
|
||||
Z80_instr_40: ; LD B,B
|
||||
@@ -41,7 +38,11 @@ Z80_instr_5B: ;
|
||||
Z80_instr_64: ; LD H,H
|
||||
Z80_instr_6D: ; LD L,L
|
||||
Z80_instr_7F: ; LD A,A
|
||||
; For interrupts (not emulated as of yet)
|
||||
Z80_illeg_DD_64: ; LD IXH,IXH
|
||||
Z80_illeg_DD_6D: ; LD IXL,IXL
|
||||
Z80_illeg_FD_64: ; LD IYH,IYH
|
||||
Z80_illeg_FD_6D: ; LD IYL,IYL
|
||||
; For interrupts (emulation not needed for CP/M)
|
||||
Z80_instr_ED_46: ; IM 0
|
||||
Z80_illeg_ED_4E: ; IM 0
|
||||
Z80_illeg_ED_66: ; IM 0
|
||||
@@ -90,7 +91,6 @@ Z80_instr_FD: +ZVM_DISPATCH Z80_vectab_FD_0, Z80_vectab_FD_1 ;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
;
|
||||
@@ -100,18 +100,12 @@ Z80_instr_FD: +ZVM_DISPATCH Z80_vectab_FD_0, Z80_vectab_FD_1 ;
|
||||
|
||||
Z80_instr_DD_CB: ; #DDCB
|
||||
Z80_instr_FD_CB: ; #FDCB
|
||||
Z80_instr_02: ; LD (BC),A
|
||||
Z80_instr_09: ; ADD HL,BC
|
||||
Z80_instr_0A: ; LD A,(BC)
|
||||
Z80_instr_12: ; LD (DE),A
|
||||
Z80_instr_19: ; ADD HL,DE
|
||||
Z80_instr_1A: ; LD A,(DE)
|
||||
Z80_instr_22: ; LD (nn),HL
|
||||
Z80_instr_29: ; ADD HL,HL
|
||||
Z80_instr_2A: ; LD HL,(nn)
|
||||
Z80_instr_32: ; LD (nn),A
|
||||
Z80_instr_39: ; ADD HL,SP
|
||||
Z80_instr_3A: ; LD A,(nn)
|
||||
Z80_instr_80: ; ADD A,B
|
||||
Z80_instr_81: ; ADD A,C
|
||||
Z80_instr_82: ; ADD A,D
|
||||
@@ -152,39 +146,13 @@ Z80_instr_BC: ; CP H
|
||||
Z80_instr_BD: ; CP L
|
||||
Z80_instr_BE: ; CP (HL)
|
||||
Z80_instr_BF: ; CP A
|
||||
Z80_instr_C0: ; RET NZ
|
||||
Z80_instr_C4: ; CALL NZ,nn
|
||||
Z80_instr_C6: ; ADD A,n
|
||||
Z80_instr_C7: ; RST 00H
|
||||
Z80_instr_C8: ; RET z
|
||||
Z80_instr_C9: ; RET
|
||||
Z80_instr_CC: ; CALL Z,nn
|
||||
Z80_instr_CD: ; CALL nn
|
||||
Z80_instr_CE: ; ADC A,n
|
||||
Z80_instr_CF: ; RST 08H
|
||||
Z80_instr_D0: ; RET NC
|
||||
Z80_instr_D4: ; CALL NC,nn
|
||||
Z80_instr_D6: ; SUB n
|
||||
Z80_instr_D7: ; RST 10H
|
||||
Z80_instr_D8: ; RET C
|
||||
Z80_instr_DC: ; CALL C,nn
|
||||
Z80_instr_DE: ; SBC A,n
|
||||
Z80_instr_DF: ; RST 18H
|
||||
Z80_instr_E0: ; RET PO
|
||||
Z80_instr_E3: ; EX (SP),HL
|
||||
Z80_instr_E4: ; CALL PO,nn
|
||||
Z80_instr_E7: ; RST 20H
|
||||
Z80_instr_E8: ; RET PE
|
||||
Z80_instr_EC: ; CALL PE,nn
|
||||
Z80_instr_EF: ; RST 28H
|
||||
Z80_instr_F0: ; RET P
|
||||
Z80_instr_F4: ; CALL P,nn
|
||||
Z80_instr_F7: ; RST 30H
|
||||
Z80_instr_F8: ; RET M
|
||||
Z80_instr_F9: ; LD SP,HL
|
||||
Z80_instr_FC: ; CALL M,nn
|
||||
Z80_instr_FE: ; CP n
|
||||
Z80_instr_FF: ; RST 38H
|
||||
Z80_instr_CB_00: ; RLC B
|
||||
Z80_instr_CB_01: ; RLC C
|
||||
Z80_instr_CB_02: ; RLC D
|
||||
@@ -247,20 +215,6 @@ Z80_instr_DD_22: ; LD (nn),IX
|
||||
Z80_instr_DD_29: ; ADD IX,IX
|
||||
Z80_instr_DD_2A: ; LD IX,(nn)
|
||||
Z80_instr_DD_39: ; ADD IX,SP
|
||||
Z80_instr_DD_46: ; LD B,(IX+d)
|
||||
Z80_instr_DD_4E: ; LD C,(IX+d)
|
||||
Z80_instr_DD_56: ; LD D,(IX+d)
|
||||
Z80_instr_DD_5E: ; LD E,(IX+d)
|
||||
Z80_instr_DD_66: ; LD H,(IX+d)
|
||||
Z80_instr_DD_6E: ; LD L,(IX+d)
|
||||
Z80_instr_DD_70: ; LD (IX+d),B
|
||||
Z80_instr_DD_71: ; LD (IX+d),C
|
||||
Z80_instr_DD_72: ; LD (IX+d),D
|
||||
Z80_instr_DD_73: ; LD (IX+d),E
|
||||
Z80_instr_DD_74: ; LD (IX+d),H
|
||||
Z80_instr_DD_75: ; LD (IX+d),L
|
||||
Z80_instr_DD_77: ; LD (IX+d),A
|
||||
Z80_instr_DD_7E: ; LD A,(IX+d)
|
||||
Z80_instr_DD_86: ; ADD A,(IX+d)
|
||||
Z80_instr_DD_8E: ; ADC A,(IX+d)
|
||||
Z80_instr_DD_96: ; SUB (IX+d)
|
||||
@@ -270,10 +224,8 @@ Z80_instr_DD_E3: ; EX (SP),IX
|
||||
Z80_instr_DD_F9: ; LD SP,IX
|
||||
Z80_instr_ED_42: ; SBC HL,BC
|
||||
Z80_instr_ED_43: ; LD (nn),BC
|
||||
Z80_instr_ED_45: ; RETN
|
||||
Z80_instr_ED_4A: ; ADC HL,BC
|
||||
Z80_instr_ED_4B: ; LD BC,(nn)
|
||||
Z80_instr_ED_4D: ; RETTI
|
||||
Z80_instr_ED_52: ; SBC HL,DE
|
||||
Z80_instr_ED_53: ; LD (nn),DE
|
||||
Z80_instr_ED_5A: ; ADC HL,DE
|
||||
@@ -308,20 +260,6 @@ Z80_instr_FD_22: ; LD (nn),IY
|
||||
Z80_instr_FD_29: ; ADD IY,IY
|
||||
Z80_instr_FD_2A: ; LD IY,(nn)
|
||||
Z80_instr_FD_39: ; ADD IY,SP
|
||||
Z80_instr_FD_46: ; LD B,(IY+d)
|
||||
Z80_instr_FD_4E: ; LD C,(IY+d)
|
||||
Z80_instr_FD_56: ; LD D,(IY+d)
|
||||
Z80_instr_FD_5E: ; LD E,(IY+d)
|
||||
Z80_instr_FD_66: ; LD H,(IY+d)
|
||||
Z80_instr_FD_6E: ; LD L,(IY+d)
|
||||
Z80_instr_FD_70: ; LD (IY+d),B
|
||||
Z80_instr_FD_71: ; LD (IY+d),C
|
||||
Z80_instr_FD_72: ; LD (IY+d),D
|
||||
Z80_instr_FD_73: ; LD (IY+d),E
|
||||
Z80_instr_FD_74: ; LD (IY+d),H
|
||||
Z80_instr_FD_75: ; LD (IY+d),L
|
||||
Z80_instr_FD_77: ; LD (IY+d),A
|
||||
Z80_instr_FD_7E: ; LD A,(IY+d)
|
||||
Z80_instr_FD_86: ; ADD A,(IY+d)
|
||||
Z80_instr_FD_8E: ; ADC A,(IY+d)
|
||||
Z80_instr_FD_96: ; SUB (IY+d)
|
||||
@@ -344,14 +282,143 @@ Z80_illeg_CB_34: ; SLL H
|
||||
Z80_illeg_CB_35: ; SLL L
|
||||
Z80_illeg_CB_36: ; SLL (HL)
|
||||
Z80_illeg_CB_37: ; SLL A
|
||||
Z80_illeg_ED_55: ; RETN
|
||||
Z80_illeg_ED_5D: ; RETN
|
||||
Z80_illeg_ED_65: ; RETN
|
||||
Z80_illeg_ED_6D: ; RETN
|
||||
Z80_illeg_ED_70: ; IN F,(C)
|
||||
Z80_illeg_ED_71: ; OUT (C),0
|
||||
Z80_illeg_ED_75: ; RETN
|
||||
Z80_illeg_ED_7D: ; RETN
|
||||
Z80_illeg_ED_63: ; LD (nn),HL
|
||||
Z80_illeg_ED_6B: ; LD HL,(nn)
|
||||
Z80_illeg_DD_84: ; ADD A,IXH
|
||||
Z80_illeg_DD_85: ; ADD A,IXL
|
||||
Z80_illeg_DD_8C: ; ADC A,IXH
|
||||
Z80_illeg_DD_8D: ; ADC A,IXL
|
||||
Z80_illeg_DD_94: ; SUB A,IXH
|
||||
Z80_illeg_DD_95: ; SUB A,IXL
|
||||
Z80_illeg_DD_9C: ; SBC A,IXH
|
||||
Z80_illeg_DD_9D: ; SBC A,IXL
|
||||
Z80_illeg_DD_BC: ; CP IXH
|
||||
Z80_illeg_DD_BD: ; CP IXL
|
||||
Z80_illeg_FD_84: ; ADD A,IYH
|
||||
Z80_illeg_FD_85: ; ADD A,IYL
|
||||
Z80_illeg_FD_8C: ; ADC A,IYH
|
||||
Z80_illeg_FD_8D: ; ADC A,IYL
|
||||
Z80_illeg_FD_94: ; SUB A,IYH
|
||||
Z80_illeg_FD_95: ; SUB A,IYL
|
||||
Z80_illeg_FD_9C: ; SBC A,IYH
|
||||
Z80_illeg_FD_9D: ; SBC A,IYL
|
||||
Z80_illeg_FD_BC: ; CP IYH
|
||||
Z80_illeg_FD_BD: ; CP IYL
|
||||
Z80_illeg_xDCB_00: ; RLC (IXY+d),B
|
||||
Z80_illeg_xDCB_01: ; RLC (IXY+d),C
|
||||
Z80_illeg_xDCB_02: ; RLC (IXY+d),D
|
||||
Z80_illeg_xDCB_03: ; RLC (IXY+d),E
|
||||
Z80_illeg_xDCB_04: ; RLC (IXY+d),H
|
||||
Z80_illeg_xDCB_05: ; RLC (IXY+d),L
|
||||
Z80_illeg_xDCB_07: ; RLC (IXY+d),A
|
||||
Z80_illeg_xDCB_08: ; RRC (IXY+d),B
|
||||
Z80_illeg_xDCB_09: ; RRC (IXY+d),C
|
||||
Z80_illeg_xDCB_0A: ; RRC (IXY+d),D
|
||||
Z80_illeg_xDCB_0B: ; RRC (IXY+d),E
|
||||
Z80_illeg_xDCB_0C: ; RRC (IXY+d),H
|
||||
Z80_illeg_xDCB_0D: ; RRC (IXY+d),L
|
||||
Z80_illeg_xDCB_0F: ; RRC (IXY+d),A
|
||||
Z80_illeg_xDCB_10: ; RL (IXY+d),B
|
||||
Z80_illeg_xDCB_11: ; RL (IXY+d),C
|
||||
Z80_illeg_xDCB_12: ; RL (IXY+d),D
|
||||
Z80_illeg_xDCB_13: ; RL (IXY+d),E
|
||||
Z80_illeg_xDCB_14: ; RL (IXY+d),H
|
||||
Z80_illeg_xDCB_15: ; RL (IXY+d),L
|
||||
Z80_illeg_xDCB_17: ; RL (IXY+d),A
|
||||
Z80_illeg_xDCB_18: ; RR (IXY+d),B
|
||||
Z80_illeg_xDCB_19: ; RR (IXY+d),C
|
||||
Z80_illeg_xDCB_1A: ; RR (IXY+d),D
|
||||
Z80_illeg_xDCB_1B: ; RR (IXY+d),E
|
||||
Z80_illeg_xDCB_1C: ; RR (IXY+d),H
|
||||
Z80_illeg_xDCB_1D: ; RR (IXY+d),L
|
||||
Z80_illeg_xDCB_1F: ; RR (IXY+d),A
|
||||
Z80_illeg_xDCB_20: ; SLA (IXY+d),B
|
||||
Z80_illeg_xDCB_21: ; SLA (IXY+d),C
|
||||
Z80_illeg_xDCB_22: ; SLA (IXY+d),D
|
||||
Z80_illeg_xDCB_23: ; SLA (IXY+d),E
|
||||
Z80_illeg_xDCB_24: ; SLA (IXY+d),H
|
||||
Z80_illeg_xDCB_25: ; SLA (IXY+d),L
|
||||
Z80_illeg_xDCB_27: ; SLA (IXY+d),A
|
||||
Z80_illeg_xDCB_28: ; SRA (IXY+d),B
|
||||
Z80_illeg_xDCB_29: ; SRA (IXY+d),C
|
||||
Z80_illeg_xDCB_2A: ; SRA (IXY+d),D
|
||||
Z80_illeg_xDCB_2B: ; SRA (IXY+d),E
|
||||
Z80_illeg_xDCB_2C: ; SRA (IXY+d),H
|
||||
Z80_illeg_xDCB_2D: ; SRA (IXY+d),L
|
||||
Z80_illeg_xDCB_2F: ; SRA (IXY+d),A
|
||||
Z80_illeg_xDCB_30: ; SLL (IXY+d),B
|
||||
Z80_illeg_xDCB_31: ; SLL (IXY+d),C
|
||||
Z80_illeg_xDCB_32: ; SLL (IXY+d),D
|
||||
Z80_illeg_xDCB_33: ; SLL (IXY+d),E
|
||||
Z80_illeg_xDCB_34: ; SLL (IXY+d),H
|
||||
Z80_illeg_xDCB_35: ; SLL (IXY+d),L
|
||||
Z80_illeg_xDCB_36: ; SLL (IXY+d)
|
||||
Z80_illeg_xDCB_37: ; SLL (IXY+d),A
|
||||
Z80_illeg_xDCB_38: ; SLR (IXY+d),B
|
||||
Z80_illeg_xDCB_39: ; SLR (IXY+d),C
|
||||
Z80_illeg_xDCB_3A: ; SLR (IXY+d),D
|
||||
Z80_illeg_xDCB_3B: ; SLR (IXY+d),E
|
||||
Z80_illeg_xDCB_3C: ; SLR (IXY+d),H
|
||||
Z80_illeg_xDCB_3D: ; SLR (IXY+d),L
|
||||
Z80_illeg_xDCB_3F: ; SLR (IXY+d),A
|
||||
Z80_illeg_xDCB_80: ; RES 0,(IXY+d),B
|
||||
Z80_illeg_xDCB_81: ; RES 0,(IXY+d),C
|
||||
Z80_illeg_xDCB_82: ; RES 0,(IXY+d),D
|
||||
Z80_illeg_xDCB_83: ; RES 0,(IXY+d),E
|
||||
Z80_illeg_xDCB_84: ; RES 0,(IXY+d),H
|
||||
Z80_illeg_xDCB_85: ; RES 0,(IXY+d),L
|
||||
Z80_illeg_xDCB_87: ; RES 0,(IXY+d),A
|
||||
Z80_illeg_xDCB_88: ; RES 1,(IXY+d),B
|
||||
Z80_illeg_xDCB_89: ; RES 1,(IXY+d),C
|
||||
Z80_illeg_xDCB_8A: ; RES 1,(IXY+d),D
|
||||
Z80_illeg_xDCB_8B: ; RES 1,(IXY+d),E
|
||||
Z80_illeg_xDCB_8C: ; RES 1,(IXY+d),H
|
||||
Z80_illeg_xDCB_8D: ; RES 1,(IXY+d),L
|
||||
Z80_illeg_xDCB_8F: ; RES 1,(IXY+d),A
|
||||
Z80_illeg_xDCB_90: ; RES 2,(IXY+d),B
|
||||
Z80_illeg_xDCB_91: ; RES 2,(IXY+d),C
|
||||
Z80_illeg_xDCB_92: ; RES 2,(IXY+d),D
|
||||
Z80_illeg_xDCB_93: ; RES 2,(IXY+d),E
|
||||
Z80_illeg_xDCB_94: ; RES 2,(IXY+d),H
|
||||
Z80_illeg_xDCB_95: ; RES 2,(IXY+d),L
|
||||
Z80_illeg_xDCB_97: ; RES 2,(IXY+d),A
|
||||
Z80_illeg_xDCB_98: ; RES 3,(IXY+d),B
|
||||
Z80_illeg_xDCB_99: ; RES 3,(IXY+d),C
|
||||
Z80_illeg_xDCB_9A: ; RES 3,(IXY+d),D
|
||||
Z80_illeg_xDCB_9B: ; RES 3,(IXY+d),E
|
||||
Z80_illeg_xDCB_9C: ; RES 3,(IXY+d),H
|
||||
Z80_illeg_xDCB_9D: ; RES 3,(IXY+d),L
|
||||
Z80_illeg_xDCB_9F: ; RES 3,(IXY+d),A
|
||||
Z80_illeg_xDCB_A0: ; RES 4,(IXY+d),B
|
||||
Z80_illeg_xDCB_A1: ; RES 4,(IXY+d),C
|
||||
Z80_illeg_xDCB_A2: ; RES 4,(IXY+d),D
|
||||
Z80_illeg_xDCB_A3: ; RES 4,(IXY+d),E
|
||||
Z80_illeg_xDCB_A4: ; RES 4,(IXY+d),H
|
||||
Z80_illeg_xDCB_A5: ; RES 4,(IXY+d),L
|
||||
Z80_illeg_xDCB_A7: ; RES 4,(IXY+d),A
|
||||
Z80_illeg_xDCB_A8: ; RES 5,(IXY+d),B
|
||||
Z80_illeg_xDCB_A9: ; RES 5,(IXY+d),C
|
||||
Z80_illeg_xDCB_AA: ; RES 5,(IXY+d),D
|
||||
Z80_illeg_xDCB_AB: ; RES 5,(IXY+d),E
|
||||
Z80_illeg_xDCB_AC: ; RES 5,(IXY+d),H
|
||||
Z80_illeg_xDCB_AD: ; RES 5,(IXY+d),L
|
||||
Z80_illeg_xDCB_AF: ; RES 5,(IXY+d),A
|
||||
Z80_illeg_xDCB_B0: ; RES 6,(IXY+d),B
|
||||
Z80_illeg_xDCB_B1: ; RES 6,(IXY+d),C
|
||||
Z80_illeg_xDCB_B2: ; RES 6,(IXY+d),D
|
||||
Z80_illeg_xDCB_B3: ; RES 6,(IXY+d),E
|
||||
Z80_illeg_xDCB_B4: ; RES 6,(IXY+d),H
|
||||
Z80_illeg_xDCB_B5: ; RES 6,(IXY+d),L
|
||||
Z80_illeg_xDCB_B7: ; RES 6,(IXY+d),A
|
||||
Z80_illeg_xDCB_B8: ; RES 7,(IXY+d),B
|
||||
Z80_illeg_xDCB_B9: ; RES 7,(IXY+d),C
|
||||
Z80_illeg_xDCB_BA: ; RES 7,(IXY+d),D
|
||||
Z80_illeg_xDCB_BB: ; RES 7,(IXY+d),E
|
||||
Z80_illeg_xDCB_BC: ; RES 7,(IXY+d),H
|
||||
Z80_illeg_xDCB_BD: ; RES 7,(IXY+d),L
|
||||
Z80_illeg_xDCB_BF: ; RES 7,(IXY+d),A
|
||||
Z80_illeg_xDCB_C0: ; SET 0,(IXY+d),B
|
||||
Z80_illeg_xDCB_C1: ; SET 0,(IXY+d),C
|
||||
Z80_illeg_xDCB_C2: ; SET 0,(IXY+d),D
|
||||
@@ -359,316 +426,55 @@ Z80_illeg_xDCB_C3: ; SET 0,(IXY+d),E
|
||||
Z80_illeg_xDCB_C4: ; SET 0,(IXY+d),H
|
||||
Z80_illeg_xDCB_C5: ; SET 0,(IXY+d),L
|
||||
Z80_illeg_xDCB_C7: ; SET 0,(IXY+d),A
|
||||
Z80_illeg_xDCB_C8: ; SET 1,(IXY+d),B
|
||||
Z80_illeg_xDCB_C9: ; SET 1,(IXY+d),C
|
||||
Z80_illeg_xDCB_CA: ; SET 1,(IXY+d),D
|
||||
Z80_illeg_xDCB_CB: ; SET 1,(IXY+d),E
|
||||
Z80_illeg_xDCB_CC: ; SET 1,(IXY+d),H
|
||||
Z80_illeg_xDCB_CD: ; SET 1,(IXY+d),L
|
||||
Z80_illeg_xDCB_CF: ; SET 1,(IXY+d),A
|
||||
Z80_illeg_xDCB_D0: ; SET 2,(IXY+d),B
|
||||
Z80_illeg_xDCB_D1: ; SET 2,(IXY+d),C
|
||||
Z80_illeg_xDCB_D2: ; SET 2,(IXY+d),D
|
||||
Z80_illeg_xDCB_D3: ; SET 2,(IXY+d),E
|
||||
Z80_illeg_xDCB_D4: ; SET 2,(IXY+d),H
|
||||
Z80_illeg_xDCB_D5: ; SET 2,(IXY+d),L
|
||||
Z80_illeg_xDCB_D7: ; SET 2,(IXY+d),A
|
||||
Z80_illeg_xDCB_D8: ; SET 3,(IXY+d),B
|
||||
Z80_illeg_xDCB_D9: ; SET 3,(IXY+d),C
|
||||
Z80_illeg_xDCB_DA: ; SET 3,(IXY+d),D
|
||||
Z80_illeg_xDCB_DB: ; SET 3,(IXY+d),E
|
||||
Z80_illeg_xDCB_DC: ; SET 3,(IXY+d),H
|
||||
Z80_illeg_xDCB_DD: ; SET 3,(IXY+d),L
|
||||
Z80_illeg_xDCB_DF: ; SET 3,(IXY+d),A
|
||||
Z80_illeg_xDCB_E0: ; SET 4,(IXY+d),B
|
||||
Z80_illeg_xDCB_E1: ; SET 4,(IXY+d),C
|
||||
Z80_illeg_xDCB_E2: ; SET 4,(IXY+d),D
|
||||
Z80_illeg_xDCB_E3: ; SET 4,(IXY+d),E
|
||||
Z80_illeg_xDCB_E4: ; SET 4,(IXY+d),H
|
||||
Z80_illeg_xDCB_E5: ; SET 4,(IXY+d),L
|
||||
Z80_illeg_xDCB_E7: ; SET 4,(IXY+d),A
|
||||
Z80_illeg_xDCB_E8: ; SET 5,(IXY+d),B
|
||||
Z80_illeg_xDCB_E9: ; SET 5,(IXY+d),C
|
||||
Z80_illeg_xDCB_EA: ; SET 5,(IXY+d),D
|
||||
Z80_illeg_xDCB_EB: ; SET 5,(IXY+d),E
|
||||
Z80_illeg_xDCB_EC: ; SET 5,(IXY+d),H
|
||||
Z80_illeg_xDCB_ED: ; SET 5,(IXY+d),L
|
||||
Z80_illeg_xDCB_EF: ; SET 5,(IXY+d),A
|
||||
Z80_illeg_xDCB_F0: ; SET 6,(IXY+d),B
|
||||
Z80_illeg_xDCB_F1: ; SET 6,(IXY+d),C
|
||||
Z80_illeg_xDCB_F2: ; SET 6,(IXY+d),D
|
||||
Z80_illeg_xDCB_F3: ; SET 6,(IXY+d),E
|
||||
Z80_illeg_xDCB_F4: ; SET 6,(IXY+d),H
|
||||
Z80_illeg_xDCB_F5: ; SET 6,(IXY+d),L
|
||||
Z80_illeg_xDCB_F7: ; SET 6,(IXY+d),A
|
||||
Z80_illeg_xDCB_F8: ; SET 7,(IXY+d),B
|
||||
Z80_illeg_xDCB_F9: ; SET 7,(IXY+d),C
|
||||
Z80_illeg_xDCB_FA: ; SET 7,(IXY+d),D
|
||||
Z80_illeg_xDCB_FB: ; SET 7,(IXY+d),E
|
||||
Z80_illeg_xDCB_FC: ; SET 7,(IXY+d),H
|
||||
Z80_illeg_xDCB_FD: ; SET 7,(IXY+d),L
|
||||
Z80_illeg_xDCB_FF: ; SET 7,(IXY+d),A
|
||||
|
||||
jmp ZVM_next ; XXX provide implementation
|
||||
|
||||
jmp ZVM_next ; XXX
|
||||
|
||||
; XXX add illegal instructions for combination of prefixes
|
||||
|
||||
; XXX include these in the table, add mnemonics
|
||||
|
||||
Z80_illeg_ED_63:
|
||||
Z80_illeg_ED_6B:
|
||||
Z80_illeg_DD_24:
|
||||
Z80_illeg_DD_25:
|
||||
Z80_illeg_DD_26:
|
||||
Z80_illeg_DD_2C:
|
||||
Z80_illeg_DD_2D:
|
||||
Z80_illeg_DD_2E:
|
||||
Z80_illeg_DD_44:
|
||||
Z80_illeg_DD_45:
|
||||
Z80_illeg_DD_4C:
|
||||
Z80_illeg_DD_4D:
|
||||
Z80_illeg_DD_54:
|
||||
Z80_illeg_DD_55:
|
||||
Z80_illeg_DD_5C:
|
||||
Z80_illeg_DD_5D:
|
||||
Z80_illeg_DD_60:
|
||||
Z80_illeg_DD_61:
|
||||
Z80_illeg_DD_62:
|
||||
Z80_illeg_DD_63:
|
||||
Z80_illeg_DD_64:
|
||||
Z80_illeg_DD_65:
|
||||
Z80_illeg_DD_67:
|
||||
Z80_illeg_DD_68:
|
||||
Z80_illeg_DD_69:
|
||||
Z80_illeg_DD_6A:
|
||||
Z80_illeg_DD_6B:
|
||||
Z80_illeg_DD_6C:
|
||||
Z80_illeg_DD_6D:
|
||||
Z80_illeg_DD_6F:
|
||||
Z80_illeg_DD_7C:
|
||||
Z80_illeg_DD_6D:
|
||||
Z80_illeg_DD_84:
|
||||
Z80_illeg_DD_85:
|
||||
Z80_illeg_DD_8C:
|
||||
Z80_illeg_DD_8D:
|
||||
Z80_illeg_DD_94:
|
||||
Z80_illeg_DD_95:
|
||||
Z80_illeg_DD_9C:
|
||||
Z80_illeg_DD_9D:
|
||||
Z80_illeg_DD_A4:
|
||||
Z80_illeg_DD_A5:
|
||||
Z80_illeg_DD_AC:
|
||||
Z80_illeg_DD_AD:
|
||||
Z80_illeg_DD_B4:
|
||||
Z80_illeg_DD_B5:
|
||||
Z80_illeg_DD_BC:
|
||||
Z80_illeg_DD_BD:
|
||||
Z80_illeg_FD_24:
|
||||
Z80_illeg_FD_25:
|
||||
Z80_illeg_FD_26:
|
||||
Z80_illeg_FD_2C:
|
||||
Z80_illeg_FD_2D:
|
||||
Z80_illeg_FD_2E:
|
||||
Z80_illeg_FD_44:
|
||||
Z80_illeg_FD_45:
|
||||
Z80_illeg_FD_4C:
|
||||
Z80_illeg_FD_4D:
|
||||
Z80_illeg_FD_54:
|
||||
Z80_illeg_FD_55:
|
||||
Z80_illeg_FD_5C:
|
||||
Z80_illeg_FD_5D:
|
||||
Z80_illeg_FD_60:
|
||||
Z80_illeg_FD_61:
|
||||
Z80_illeg_FD_62:
|
||||
Z80_illeg_FD_63:
|
||||
Z80_illeg_FD_64:
|
||||
Z80_illeg_FD_65:
|
||||
Z80_illeg_FD_67:
|
||||
Z80_illeg_FD_68:
|
||||
Z80_illeg_FD_69:
|
||||
Z80_illeg_FD_6A:
|
||||
Z80_illeg_FD_6B:
|
||||
Z80_illeg_FD_6C:
|
||||
Z80_illeg_FD_6D:
|
||||
Z80_illeg_FD_6F:
|
||||
Z80_illeg_FD_7C:
|
||||
Z80_illeg_FD_6D:
|
||||
Z80_illeg_FD_84:
|
||||
Z80_illeg_FD_85:
|
||||
Z80_illeg_FD_8C:
|
||||
Z80_illeg_FD_8D:
|
||||
Z80_illeg_FD_94:
|
||||
Z80_illeg_FD_95:
|
||||
Z80_illeg_FD_9C:
|
||||
Z80_illeg_FD_9D:
|
||||
Z80_illeg_FD_A4:
|
||||
Z80_illeg_FD_A5:
|
||||
Z80_illeg_FD_AC:
|
||||
Z80_illeg_FD_AD:
|
||||
Z80_illeg_FD_B4:
|
||||
Z80_illeg_FD_B5:
|
||||
Z80_illeg_FD_BC:
|
||||
Z80_illeg_FD_BD:
|
||||
Z80_illeg_xDCB_00:
|
||||
Z80_illeg_xDCB_01:
|
||||
Z80_illeg_xDCB_02:
|
||||
Z80_illeg_xDCB_03:
|
||||
Z80_illeg_xDCB_04:
|
||||
Z80_illeg_xDCB_05:
|
||||
Z80_illeg_xDCB_07:
|
||||
Z80_illeg_xDCB_08:
|
||||
Z80_illeg_xDCB_09:
|
||||
Z80_illeg_xDCB_0A:
|
||||
Z80_illeg_xDCB_0B:
|
||||
Z80_illeg_xDCB_0C:
|
||||
Z80_illeg_xDCB_0D:
|
||||
Z80_illeg_xDCB_0F:
|
||||
Z80_illeg_xDCB_10:
|
||||
Z80_illeg_xDCB_11:
|
||||
Z80_illeg_xDCB_12:
|
||||
Z80_illeg_xDCB_13:
|
||||
Z80_illeg_xDCB_14:
|
||||
Z80_illeg_xDCB_15:
|
||||
Z80_illeg_xDCB_17:
|
||||
Z80_illeg_xDCB_18:
|
||||
Z80_illeg_xDCB_19:
|
||||
Z80_illeg_xDCB_1A:
|
||||
Z80_illeg_xDCB_1B:
|
||||
Z80_illeg_xDCB_1C:
|
||||
Z80_illeg_xDCB_1D:
|
||||
Z80_illeg_xDCB_1F:
|
||||
Z80_illeg_xDCB_20:
|
||||
Z80_illeg_xDCB_21:
|
||||
Z80_illeg_xDCB_22:
|
||||
Z80_illeg_xDCB_23:
|
||||
Z80_illeg_xDCB_24:
|
||||
Z80_illeg_xDCB_25:
|
||||
Z80_illeg_xDCB_27:
|
||||
Z80_illeg_xDCB_28:
|
||||
Z80_illeg_xDCB_29:
|
||||
Z80_illeg_xDCB_2A:
|
||||
Z80_illeg_xDCB_2B:
|
||||
Z80_illeg_xDCB_2C:
|
||||
Z80_illeg_xDCB_2D:
|
||||
Z80_illeg_xDCB_2F:
|
||||
Z80_illeg_xDCB_30:
|
||||
Z80_illeg_xDCB_31:
|
||||
Z80_illeg_xDCB_32:
|
||||
Z80_illeg_xDCB_33:
|
||||
Z80_illeg_xDCB_34:
|
||||
Z80_illeg_xDCB_35:
|
||||
Z80_illeg_xDCB_36:
|
||||
Z80_illeg_xDCB_37:
|
||||
Z80_illeg_xDCB_38:
|
||||
Z80_illeg_xDCB_39:
|
||||
Z80_illeg_xDCB_3A:
|
||||
Z80_illeg_xDCB_3B:
|
||||
Z80_illeg_xDCB_3C:
|
||||
Z80_illeg_xDCB_3D:
|
||||
Z80_illeg_xDCB_3F:
|
||||
Z80_illeg_xDCB_40:
|
||||
Z80_illeg_xDCB_41:
|
||||
Z80_illeg_xDCB_42:
|
||||
Z80_illeg_xDCB_43:
|
||||
Z80_illeg_xDCB_44:
|
||||
Z80_illeg_xDCB_45:
|
||||
Z80_illeg_xDCB_47:
|
||||
Z80_illeg_xDCB_48:
|
||||
Z80_illeg_xDCB_49:
|
||||
Z80_illeg_xDCB_4A:
|
||||
Z80_illeg_xDCB_4B:
|
||||
Z80_illeg_xDCB_4C:
|
||||
Z80_illeg_xDCB_4D:
|
||||
Z80_illeg_xDCB_4F:
|
||||
Z80_illeg_xDCB_50:
|
||||
Z80_illeg_xDCB_51:
|
||||
Z80_illeg_xDCB_52:
|
||||
Z80_illeg_xDCB_53:
|
||||
Z80_illeg_xDCB_54:
|
||||
Z80_illeg_xDCB_55:
|
||||
Z80_illeg_xDCB_57:
|
||||
Z80_illeg_xDCB_58:
|
||||
Z80_illeg_xDCB_59:
|
||||
Z80_illeg_xDCB_5A:
|
||||
Z80_illeg_xDCB_5B:
|
||||
Z80_illeg_xDCB_5C:
|
||||
Z80_illeg_xDCB_5D:
|
||||
Z80_illeg_xDCB_5F:
|
||||
Z80_illeg_xDCB_60:
|
||||
Z80_illeg_xDCB_61:
|
||||
Z80_illeg_xDCB_62:
|
||||
Z80_illeg_xDCB_63:
|
||||
Z80_illeg_xDCB_64:
|
||||
Z80_illeg_xDCB_65:
|
||||
Z80_illeg_xDCB_67:
|
||||
Z80_illeg_xDCB_68:
|
||||
Z80_illeg_xDCB_69:
|
||||
Z80_illeg_xDCB_6A:
|
||||
Z80_illeg_xDCB_6B:
|
||||
Z80_illeg_xDCB_6C:
|
||||
Z80_illeg_xDCB_6D:
|
||||
Z80_illeg_xDCB_6F:
|
||||
Z80_illeg_xDCB_70:
|
||||
Z80_illeg_xDCB_71:
|
||||
Z80_illeg_xDCB_72:
|
||||
Z80_illeg_xDCB_73:
|
||||
Z80_illeg_xDCB_74:
|
||||
Z80_illeg_xDCB_75:
|
||||
Z80_illeg_xDCB_77:
|
||||
Z80_illeg_xDCB_80:
|
||||
Z80_illeg_xDCB_81:
|
||||
Z80_illeg_xDCB_82:
|
||||
Z80_illeg_xDCB_83:
|
||||
Z80_illeg_xDCB_84:
|
||||
Z80_illeg_xDCB_85:
|
||||
Z80_illeg_xDCB_87:
|
||||
Z80_illeg_xDCB_88:
|
||||
Z80_illeg_xDCB_89:
|
||||
Z80_illeg_xDCB_8A:
|
||||
Z80_illeg_xDCB_8B:
|
||||
Z80_illeg_xDCB_8C:
|
||||
Z80_illeg_xDCB_8D:
|
||||
Z80_illeg_xDCB_8F:
|
||||
Z80_illeg_xDCB_90:
|
||||
Z80_illeg_xDCB_91:
|
||||
Z80_illeg_xDCB_92:
|
||||
Z80_illeg_xDCB_93:
|
||||
Z80_illeg_xDCB_94:
|
||||
Z80_illeg_xDCB_95:
|
||||
Z80_illeg_xDCB_97:
|
||||
Z80_illeg_xDCB_98:
|
||||
Z80_illeg_xDCB_99:
|
||||
Z80_illeg_xDCB_9A:
|
||||
Z80_illeg_xDCB_9B:
|
||||
Z80_illeg_xDCB_9C:
|
||||
Z80_illeg_xDCB_9D:
|
||||
Z80_illeg_xDCB_9F:
|
||||
Z80_illeg_xDCB_A0:
|
||||
Z80_illeg_xDCB_A1:
|
||||
Z80_illeg_xDCB_A2:
|
||||
Z80_illeg_xDCB_A3:
|
||||
Z80_illeg_xDCB_A4:
|
||||
Z80_illeg_xDCB_A5:
|
||||
Z80_illeg_xDCB_A7:
|
||||
Z80_illeg_xDCB_A8:
|
||||
Z80_illeg_xDCB_A9:
|
||||
Z80_illeg_xDCB_AA:
|
||||
Z80_illeg_xDCB_AB:
|
||||
Z80_illeg_xDCB_AC:
|
||||
Z80_illeg_xDCB_AD:
|
||||
Z80_illeg_xDCB_AF:
|
||||
Z80_illeg_xDCB_B0:
|
||||
Z80_illeg_xDCB_B1:
|
||||
Z80_illeg_xDCB_B2:
|
||||
Z80_illeg_xDCB_B3:
|
||||
Z80_illeg_xDCB_B4:
|
||||
Z80_illeg_xDCB_B5:
|
||||
Z80_illeg_xDCB_B7:
|
||||
Z80_illeg_xDCB_B8:
|
||||
Z80_illeg_xDCB_B9:
|
||||
Z80_illeg_xDCB_BA:
|
||||
Z80_illeg_xDCB_BB:
|
||||
Z80_illeg_xDCB_BC:
|
||||
Z80_illeg_xDCB_BD:
|
||||
Z80_illeg_xDCB_BF:
|
||||
Z80_illeg_xDCB_C8:
|
||||
Z80_illeg_xDCB_C9:
|
||||
Z80_illeg_xDCB_CA:
|
||||
Z80_illeg_xDCB_CB:
|
||||
Z80_illeg_xDCB_CC:
|
||||
Z80_illeg_xDCB_CD:
|
||||
Z80_illeg_xDCB_CF:
|
||||
Z80_illeg_xDCB_D0:
|
||||
Z80_illeg_xDCB_D1:
|
||||
Z80_illeg_xDCB_D2:
|
||||
Z80_illeg_xDCB_D3:
|
||||
Z80_illeg_xDCB_D4:
|
||||
Z80_illeg_xDCB_D5:
|
||||
Z80_illeg_xDCB_D7:
|
||||
Z80_illeg_xDCB_D8:
|
||||
Z80_illeg_xDCB_D9:
|
||||
Z80_illeg_xDCB_DA:
|
||||
Z80_illeg_xDCB_DB:
|
||||
Z80_illeg_xDCB_DC:
|
||||
Z80_illeg_xDCB_DD:
|
||||
Z80_illeg_xDCB_DF:
|
||||
Z80_illeg_xDCB_E0:
|
||||
Z80_illeg_xDCB_E1:
|
||||
Z80_illeg_xDCB_E2:
|
||||
Z80_illeg_xDCB_E3:
|
||||
Z80_illeg_xDCB_E4:
|
||||
Z80_illeg_xDCB_E5:
|
||||
Z80_illeg_xDCB_E7:
|
||||
Z80_illeg_xDCB_E8:
|
||||
Z80_illeg_xDCB_E9:
|
||||
Z80_illeg_xDCB_EA:
|
||||
Z80_illeg_xDCB_EB:
|
||||
Z80_illeg_xDCB_EC:
|
||||
Z80_illeg_xDCB_ED:
|
||||
Z80_illeg_xDCB_EF:
|
||||
Z80_illeg_xDCB_F0:
|
||||
Z80_illeg_xDCB_F1:
|
||||
Z80_illeg_xDCB_F2:
|
||||
Z80_illeg_xDCB_F3:
|
||||
Z80_illeg_xDCB_F4:
|
||||
Z80_illeg_xDCB_F5:
|
||||
Z80_illeg_xDCB_F7:
|
||||
Z80_illeg_xDCB_F8:
|
||||
Z80_illeg_xDCB_F9:
|
||||
Z80_illeg_xDCB_FA:
|
||||
Z80_illeg_xDCB_FB:
|
||||
Z80_illeg_xDCB_FC:
|
||||
Z80_illeg_xDCB_FD:
|
||||
Z80_illeg_xDCB_FF:
|
||||
Reference in new issue
Block a user