more work on Z80 opcodes
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FeralChild64 authored and FeralChild64 committed
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@@ -59,153 +59,194 @@ Z80_instr_7B: +Z80_LD_REGn_REGn REG_A, REG_E ;
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Z80_instr_7C: +Z80_LD_REGn_REGn REG_A, REG_H ; LD A,H
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Z80_instr_7D: +Z80_LD_REGn_REGn REG_A, REG_L ; LD A,L
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;
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; load register with immediate value
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;
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Z80_illeg_DD_44: +Z80_LD_REGn_REGn REG_B, REG_IXH ; LD B,IXH
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Z80_illeg_DD_45: +Z80_LD_REGn_REGn REG_B, REG_IXL ; LD B,IXL
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Z80_illeg_DD_4C: +Z80_LD_REGn_REGn REG_C, REG_IXH ; LD C,IXH
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Z80_illeg_DD_4D: +Z80_LD_REGn_REGn REG_C, REG_IXL ; LD C,IXL
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Z80_illeg_DD_54: +Z80_LD_REGn_REGn REG_D, REG_IXH ; LD D,IXH
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Z80_illeg_DD_55: +Z80_LD_REGn_REGn REG_D, REG_IXL ; LD D,IXL
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Z80_illeg_DD_5C: +Z80_LD_REGn_REGn REG_E, REG_IXH ; LD E,IXH
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Z80_illeg_DD_5D: +Z80_LD_REGn_REGn REG_E, REG_IXL ; LD E,IXL
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Z80_illeg_DD_7C: +Z80_LD_REGn_REGn REG_A, REG_IXH ; LD A,IXH
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Z80_illeg_DD_7D: +Z80_LD_REGn_REGn REG_A, REG_IXL ; LD A,IXL
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Z80_instr_06: ; LD B,n
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Z80_illeg_FD_44: +Z80_LD_REGn_REGn REG_B, REG_IYH ; LD B,IYH
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Z80_illeg_FD_45: +Z80_LD_REGn_REGn REG_B, REG_IYL ; LD B,IYL
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Z80_illeg_FD_4C: +Z80_LD_REGn_REGn REG_C, REG_IYH ; LD C,IYH
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Z80_illeg_FD_4D: +Z80_LD_REGn_REGn REG_C, REG_IYL ; LD C,IYL
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Z80_illeg_FD_54: +Z80_LD_REGn_REGn REG_D, REG_IYH ; LD D,IYH
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Z80_illeg_FD_55: +Z80_LD_REGn_REGn REG_D, REG_IYL ; LD D,IYL
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Z80_illeg_FD_5C: +Z80_LD_REGn_REGn REG_E, REG_IYH ; LD E,IYH
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Z80_illeg_FD_5D: +Z80_LD_REGn_REGn REG_E, REG_IYL ; LD E,IYL
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Z80_illeg_FD_7C: +Z80_LD_REGn_REGn REG_A, REG_IYH ; LD A,IYH
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Z80_illeg_FD_7D: +Z80_LD_REGn_REGn REG_A, REG_IYL ; LD A,IYL
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Z80_illeg_DD_60: +Z80_LD_REGn_REGn REG_IXH, REG_B ; LD IXH,B
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Z80_illeg_DD_61: +Z80_LD_REGn_REGn REG_IXH, REG_C ; LD IXH,C
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Z80_illeg_DD_62: +Z80_LD_REGn_REGn REG_IXH, REG_D ; LD IXH,D
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Z80_illeg_DD_63: +Z80_LD_REGn_REGn REG_IXH, REG_E ; LD IXH,E
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Z80_illeg_DD_65: +Z80_LD_REGn_REGn REG_IXH, REG_IXL ; LD IXH,IXL
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Z80_illeg_DD_67: +Z80_LD_REGn_REGn REG_IXH, REG_A ; LD IXH,A
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Z80_illeg_DD_68: +Z80_LD_REGn_REGn REG_IXL, REG_B ; LD IXL,B
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Z80_illeg_DD_69: +Z80_LD_REGn_REGn REG_IXL, REG_C ; LD IXL,C
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Z80_illeg_DD_6A: +Z80_LD_REGn_REGn REG_IXL, REG_D ; LD IXL,D
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Z80_illeg_DD_6B: +Z80_LD_REGn_REGn REG_IXL, REG_E ; LD IXL,E
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Z80_illeg_DD_6C: +Z80_LD_REGn_REGn REG_IXL, REG_IXH ; LD IXL,IXH
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Z80_illeg_DD_6F: +Z80_LD_REGn_REGn REG_IXL, REG_A ; LD IXL,A
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Z80_illeg_FD_60: +Z80_LD_REGn_REGn REG_IYH, REG_B ; LD IYH,B
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Z80_illeg_FD_61: +Z80_LD_REGn_REGn REG_IYH, REG_C ; LD IYH,C
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Z80_illeg_FD_62: +Z80_LD_REGn_REGn REG_IYH, REG_D ; LD IYH,D
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Z80_illeg_FD_63: +Z80_LD_REGn_REGn REG_IYH, REG_E ; LD IYH,E
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Z80_illeg_FD_65: +Z80_LD_REGn_REGn REG_IYH, REG_IYL ; LD IYH,IYL
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Z80_illeg_FD_67: +Z80_LD_REGn_REGn REG_IYH, REG_A ; LD IYH,A
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Z80_illeg_FD_68: +Z80_LD_REGn_REGn REG_IYL, REG_B ; LD IYL,B
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Z80_illeg_FD_69: +Z80_LD_REGn_REGn REG_IYL, REG_C ; LD IYL,C
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Z80_illeg_FD_6A: +Z80_LD_REGn_REGn REG_IYL, REG_D ; LD IYL,D
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Z80_illeg_FD_6B: +Z80_LD_REGn_REGn REG_IYL, REG_E ; LD IYL,E
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Z80_illeg_FD_6C: +Z80_LD_REGn_REGn REG_IYL, REG_IYH ; LD IYL,IYH
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Z80_illeg_FD_6F: +Z80_LD_REGn_REGn REG_IYL, REG_A ; LD IYL,A
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!macro Z80_LD_REGn_n .REGn {
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jsr (VEC_fetch_value)
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sta REG_B
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sta .REGn
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jmp ZVM_next
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}
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Z80_instr_0E: ; LD C,n
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Z80_instr_06: +Z80_LD_REGn_n REG_B ; LD B,n
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Z80_instr_0E: +Z80_LD_REGn_n REG_C ; LD C,n
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Z80_instr_16: +Z80_LD_REGn_n REG_D ; LD D,n
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Z80_instr_1E: +Z80_LD_REGn_n REG_E ; LD E,n
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Z80_instr_26: +Z80_LD_REGn_n REG_H ; LD H,n
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Z80_instr_2E: +Z80_LD_REGn_n REG_L ; LD L,n
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Z80_instr_3E: +Z80_LD_REGn_n REG_A ; LD A,n
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jsr (VEC_fetch_value)
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sta REG_C
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jmp ZVM_next
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Z80_instr_16: ; LD D,n
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jsr (VEC_fetch_value)
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sta REG_D
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jmp ZVM_next
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Z80_instr_1E: ; LD E,n
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jsr (VEC_fetch_value)
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sta REG_E
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jmp ZVM_next
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Z80_instr_26: ; LD H,n
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jsr (VEC_fetch_value)
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sta REG_H
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jmp ZVM_next
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Z80_instr_2E: ; LD L,n
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jsr (VEC_fetch_value)
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sta REG_L
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jmp ZVM_next
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Z80_instr_3E: ; LD A,n
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jsr (VEC_fetch_value)
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sta REG_A
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jmp ZVM_next
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;
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; load register with memory content (via HL)
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;
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Z80_instr_46: ; LD B,(HL)
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Z80_illeg_DD_26: +Z80_LD_REGn_n REG_IXH ; LD IXH,n
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Z80_illeg_DD_2E: +Z80_LD_REGn_n REG_IXL ; LD IXL,n
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Z80_illeg_FD_26: +Z80_LD_REGn_n REG_IYH ; LD IYH,n
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Z80_illeg_FD_2E: +Z80_LD_REGn_n REG_IYL ; LD IYL,n
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!macro Z80_LD_REGn_VIA_HL .REGn {
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jsr (VEC_fetch_via_HL)
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sta REG_B
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sta .REGn
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jmp ZVM_next
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}
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Z80_instr_4E: ; LD C,(HL)
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Z80_instr_46: +Z80_LD_REGn_VIA_HL REG_B ; LD B,(HL)
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Z80_instr_4E: +Z80_LD_REGn_VIA_HL REG_C ; LD C,(HL)
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Z80_instr_56: +Z80_LD_REGn_VIA_HL REG_D ; LD D,(HL)
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Z80_instr_5E: +Z80_LD_REGn_VIA_HL REG_E ; LD E,(HL)
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Z80_instr_66: +Z80_LD_REGn_VIA_HL REG_H ; LD H,(HL)
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Z80_instr_6E: +Z80_LD_REGn_VIA_HL REG_L ; LD L,(HL)
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Z80_instr_7E: +Z80_LD_REGn_VIA_HL REG_A ; LD A,(HL)
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jsr (VEC_fetch_via_HL)
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sta REG_C
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jmp ZVM_next
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Z80_instr_56: ; LD D,(HL)
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jsr (VEC_fetch_via_HL)
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sta REG_D
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jmp ZVM_next
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Z80_instr_5E: ; LD E,(HL)
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jsr (VEC_fetch_via_HL)
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sta REG_E
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jmp ZVM_next
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Z80_instr_66: ; LD H,(HL)
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jsr (VEC_fetch_via_HL)
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sta REG_H
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jmp ZVM_next
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Z80_instr_6E: ; LD L,(HL)
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jsr (VEC_fetch_via_HL)
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sta REG_L
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jmp ZVM_next
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Z80_instr_7E: ; LD A,(HL)
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jsr (VEC_fetch_via_HL)
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sta REG_A
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jmp ZVM_next
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; XXX put here LD r,(IX+d) family
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; XXX put here LD r,(IY+d) family
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;
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; load memory content (via HL) with register
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;
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Z80_instr_70: ; LD (HL),B
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lda REG_B
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!macro Z80_LD_VIA_HL_REGn .REGn {
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lda .REGn
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jsr (VEC_store_via_HL)
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jmp ZVM_next
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}
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Z80_instr_71: ; LD (HL),C
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Z80_instr_70: +Z80_LD_VIA_HL_REGn REG_B ; LD (HL),B
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Z80_instr_71: +Z80_LD_VIA_HL_REGn REG_C ; LD (HL),C
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Z80_instr_72: +Z80_LD_VIA_HL_REGn REG_D ; LD (HL),D
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Z80_instr_73: +Z80_LD_VIA_HL_REGn REG_E ; LD (HL),E
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Z80_instr_74: +Z80_LD_VIA_HL_REGn REG_H ; LD (HL),H
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Z80_instr_75: +Z80_LD_VIA_HL_REGn REG_L ; LD (HL),L
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Z80_instr_77: +Z80_LD_VIA_HL_REGn REG_A ; LD (HL),A
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lda REG_C
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jsr (VEC_store_via_HL)
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jmp ZVM_next
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Z80_instr_72: ; LD (HL),D
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lda REG_D
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jsr (VEC_store_via_HL)
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jmp ZVM_next
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Z80_instr_73: ; LD (HL),E
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lda REG_E
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jsr (VEC_store_via_HL)
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jmp ZVM_next
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Z80_instr_74: ; LD (HL),H
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lda REG_H
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jsr (VEC_store_via_HL)
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jmp ZVM_next
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Z80_instr_75: ; LD (HL),L
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lda REG_L
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jsr (VEC_store_via_HL)
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jmp ZVM_next
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Z80_instr_77: ; LD (HL),A
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Z80_instr_02: ; LD (BC),A
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lda REG_A
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jsr (VEC_store_via_HL)
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jsr (VEC_store_via_BC)
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jmp ZVM_next
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; XXX put here LD (IX+d),r family
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; XXX put here LD (IY+d),r family
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Z80_instr_0A: ; LD A,(BC)
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;
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; load memory content (via HL) with immediate value
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;
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jsr (VEC_fetch_via_BC)
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sta REG_A
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jmp ZVM_next
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Z80_instr_12: ; LD (DE),A
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lda REG_A
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jsr (VEC_store_via_DE)
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jmp ZVM_next
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Z80_instr_1A: ; LD A,(DE)
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jsr (VEC_fetch_via_DE)
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sta REG_A
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jmp ZVM_next
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Z80_instr_32: ; LD (nn),A
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lda REG_A
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jsr (VEC_store_via_nn)
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jmp ZVM_next
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Z80_instr_3A: ; LD A,(nn)
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jsr (VEC_fetch_via_nn)
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sta REG_A
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jmp ZVM_next
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!macro Z80_LD_REGn_VIA_IX_d .REGn {
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jsr (VEC_fetch_via_IX_d)
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sta .REGn
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jmp ZVM_next
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}
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Z80_instr_DD_46: +Z80_LD_REGn_VIA_IX_d REG_B ; LD B,(IX+d)
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Z80_instr_DD_4E: +Z80_LD_REGn_VIA_IX_d REG_C ; LD C,(IX+d)
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Z80_instr_DD_56: +Z80_LD_REGn_VIA_IX_d REG_D ; LD D,(IX+d)
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Z80_instr_DD_5E: +Z80_LD_REGn_VIA_IX_d REG_E ; LD E,(IX+d)
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Z80_instr_DD_66: +Z80_LD_REGn_VIA_IX_d REG_H ; LD H,(IX+d)
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Z80_instr_DD_6E: +Z80_LD_REGn_VIA_IX_d REG_L ; LD L,(IX+d)
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Z80_instr_DD_7E: +Z80_LD_REGn_VIA_IX_d REG_A ; LD A,(IX+d)
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!macro Z80_LD_REGn_VIA_IY_d .REGn {
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jsr (VEC_fetch_via_IY_d)
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sta .REGn
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jmp ZVM_next
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}
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Z80_instr_FD_46: +Z80_LD_REGn_VIA_IY_d REG_B ; LD B,(IY+d)
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Z80_instr_FD_4E: +Z80_LD_REGn_VIA_IY_d REG_C ; LD C,(IY+d)
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Z80_instr_FD_56: +Z80_LD_REGn_VIA_IY_d REG_D ; LD D,(IY+d)
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Z80_instr_FD_5E: +Z80_LD_REGn_VIA_IY_d REG_E ; LD E,(IY+d)
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Z80_instr_FD_66: +Z80_LD_REGn_VIA_IY_d REG_H ; LD H,(IY+d)
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Z80_instr_FD_6E: +Z80_LD_REGn_VIA_IY_d REG_L ; LD L,(IY+d)
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Z80_instr_FD_7E: +Z80_LD_REGn_VIA_IY_d REG_A ; LD A,(IY+d)
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!macro Z80_LD_VIA_IX_d_REG_n .REGn {
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lda .REGn
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jsr (VEC_store_via_IX_d)
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jmp ZVM_next
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}
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Z80_instr_DD_70: +Z80_LD_VIA_IX_d_REG_n REG_B ; LD (IX+d),B
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Z80_instr_DD_71: +Z80_LD_VIA_IX_d_REG_n REG_C ; LD (IX+d),C
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Z80_instr_DD_72: +Z80_LD_VIA_IX_d_REG_n REG_D ; LD (IX+d),D
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Z80_instr_DD_73: +Z80_LD_VIA_IX_d_REG_n REG_E ; LD (IX+d),E
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Z80_instr_DD_74: +Z80_LD_VIA_IX_d_REG_n REG_H ; LD (IX+d),H
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Z80_instr_DD_75: +Z80_LD_VIA_IX_d_REG_n REG_L ; LD (IX+d),L
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Z80_instr_DD_77: +Z80_LD_VIA_IX_d_REG_n REG_A ; LD (IX+d),A
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!macro Z80_LD_VIA_IY_d_REG_n .REGn {
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lda .REGn
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jsr (VEC_store_via_IY_d)
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jmp ZVM_next
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}
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Z80_instr_FD_70: +Z80_LD_VIA_IY_d_REG_n REG_B ; LD (IY+d),B
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Z80_instr_FD_71: +Z80_LD_VIA_IY_d_REG_n REG_C ; LD (IY+d),C
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Z80_instr_FD_72: +Z80_LD_VIA_IY_d_REG_n REG_D ; LD (IY+d),D
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Z80_instr_FD_73: +Z80_LD_VIA_IY_d_REG_n REG_E ; LD (IY+d),E
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Z80_instr_FD_74: +Z80_LD_VIA_IY_d_REG_n REG_H ; LD (IY+d),H
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Z80_instr_FD_75: +Z80_LD_VIA_IY_d_REG_n REG_L ; LD (IY+d),L
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Z80_instr_FD_77: +Z80_LD_VIA_IY_d_REG_n REG_A ; LD (IY+d),A
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Z80_instr_36: ; LD (HL),n
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@@ -213,10 +254,6 @@ Z80_instr_36: ; LD (HL),n
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jsr (VEC_store_via_HL)
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jmp ZVM_next
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; XXX put here LD (IX+d),n family
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; XXX put here LD (IY+d),n family
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; XXX put here LD A,(BC) / LD A,(DE) / LD A,(nn) / LD (BC), A / LD (DE),A / LD (nn),A
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Z80_instr_ED_57: ; LD A,I
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lda REG_F
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