more work on Z80 opcodes
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@@ -60,6 +60,10 @@ Z80_instr_A2: +Z80_AND_REGn REG_D ;
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Z80_instr_A3: +Z80_AND_REGn REG_E ; AND E
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Z80_instr_A4: +Z80_AND_REGn REG_H ; AND H
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Z80_instr_A5: +Z80_AND_REGn REG_L ; AND L
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Z80_illeg_DD_A4: +Z80_AND_REGn REG_IXH ; AND IXH
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Z80_illeg_DD_A5: +Z80_AND_REGn REG_IXL ; AND IXL
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Z80_illeg_FD_A4: +Z80_AND_REGn REG_IYH ; AND IYH
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Z80_illeg_FD_A5: +Z80_AND_REGn REG_IXL ; AND IYL
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Z80_instr_A6: +Z80_AND_VIA_HL ; AND (HL)
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Z80_instr_A7: +Z80_AND_SELF ; AND A
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Z80_instr_E6: +Z80_AND_n ; AND n
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@@ -118,6 +122,10 @@ Z80_instr_B2: +Z80_OR_REGn REG_D ;
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Z80_instr_B3: +Z80_OR_REGn REG_E ; OR E
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Z80_instr_B4: +Z80_OR_REGn REG_H ; OR H
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Z80_instr_B5: +Z80_OR_REGn REG_L ; OR L
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Z80_illeg_DD_B4: +Z80_OR_REGn REG_IXH ; OR IXH
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Z80_illeg_DD_B5: +Z80_OR_REGn REG_IXL ; OR IXL
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Z80_illeg_FD_B4: +Z80_OR_REGn REG_IYH ; OR IYH
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Z80_illeg_FD_B5: +Z80_OR_REGn REG_IYL ; OR IYL
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Z80_instr_B6: +Z80_OR_VIA_HL ; OR (HL)
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Z80_instr_B7: +Z80_OR_SELF ; OR A
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Z80_instr_F6: +Z80_OR_n ; OR n
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@@ -173,51 +181,34 @@ Z80_instr_AA: +Z80_XOR_REGn REG_D ;
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Z80_instr_AB: +Z80_XOR_REGn REG_E ; XOR E
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Z80_instr_AC: +Z80_XOR_REGn REG_H ; XOR H
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Z80_instr_AD: +Z80_XOR_REGn REG_L ; XOR L
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Z80_illeg_DD_AC: +Z80_XOR_REGn REG_IXH ; XOR IXH
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Z80_illeg_DD_AD: +Z80_XOR_REGn REG_IXL ; XOR IXL
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Z80_illeg_FD_AC: +Z80_XOR_REGn REG_IYH ; XOR IYH
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Z80_illeg_FD_AD: +Z80_XOR_REGn REG_IXL ; XOR IYL
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Z80_instr_AE: +Z80_XOR_VIA_HL ; XOR (HL)
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Z80_instr_AF: +Z80_XOR_SELF ; XOR A
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Z80_instr_EE: +Z80_XOR_n ; XOR n
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Z80_instr_DD_AE: +Z80_XOR_VIA_IX_d ; XOR (IX+d)
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Z80_instr_FD_AE: +Z80_XOR_VIA_IY_d ; XOR (IY+d)
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; XXX put CP instructions here
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Z80_instr_04: ; INC B
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ldx REG_B
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inc REG_B
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!macro Z80_INC_REG_n .REG_n {
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ldx .REG_n
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inc .REG_n
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bra Z80_common_INC
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}
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Z80_instr_0C: ; INC C
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Z80_instr_04: +Z80_INC_REG_n REG_B ; INC B
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Z80_instr_0C: +Z80_INC_REG_n REG_C ; INC C
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Z80_instr_14: +Z80_INC_REG_n REG_D ; INC D
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Z80_instr_1C: +Z80_INC_REG_n REG_E ; INC E
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Z80_instr_24: +Z80_INC_REG_n REG_H ; INC H
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Z80_instr_2C: +Z80_INC_REG_n REG_L ; INC L
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Z80_illeg_DD_24: +Z80_INC_REG_n REG_IXH ; INC IXH
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Z80_illeg_DD_2C: +Z80_INC_REG_n REG_IXL ; INC IXL
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Z80_illeg_FD_24: +Z80_INC_REG_n REG_IYH ; INC IYH
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Z80_illeg_FD_2C: +Z80_INC_REG_n REG_IYL ; INC IYL
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ldx REG_C
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inc REG_C
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bra Z80_common_INC
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Z80_instr_14: ; INC D
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ldx REG_D
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inc REG_D
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bra Z80_common_INC
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Z80_instr_1C: ; INC E
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ldx REG_E
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inc REG_E
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bra Z80_common_INC
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Z80_instr_24: ; INC H
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ldx REG_H
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inc REG_H
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bra Z80_common_INC
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Z80_instr_2C: ; INC L
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ldx REG_L
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inc REG_L
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bra Z80_common_INC
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Z80_instr_3C: ; INC A
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Z80_instr_3C: ; INC A
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ldx REG_A
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inc REG_A
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@@ -256,43 +247,24 @@ Z80_instr_FD_34: ; INC (IY+d)
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sta [PTR_DATA],z
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bra Z80_common_INC
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Z80_instr_05: ; DEC B
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ldx REG_B
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dec REG_B
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!macro Z80_DEC_REG_n .REG_n {
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ldx .REG_n
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dec .REG_n
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bra Z80_common_DEC
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}
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Z80_instr_0D: ; DEC C
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Z80_instr_05: +Z80_DEC_REG_n REG_B ; DEC B
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Z80_instr_0D: +Z80_DEC_REG_n REG_C ; DEC C
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Z80_instr_15: +Z80_DEC_REG_n REG_D ; DEC D
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Z80_instr_1D: +Z80_DEC_REG_n REG_E ; DEC E
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Z80_instr_25: +Z80_DEC_REG_n REG_H ; DEC H
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Z80_instr_2D: +Z80_DEC_REG_n REG_L ; DEC L
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Z80_illeg_DD_25: +Z80_DEC_REG_n REG_IXH ; DEC IXH
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Z80_illeg_DD_2D: +Z80_DEC_REG_n REG_IXL ; DEC IXL
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Z80_illeg_FD_25: +Z80_DEC_REG_n REG_IYH ; DEC IYH
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Z80_illeg_FD_2D: +Z80_DEC_REG_n REG_IYL ; DEC IYL
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ldx REG_C
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dec REG_C
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bra Z80_common_DEC
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Z80_instr_15: ; DEC D
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ldx REG_D
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dec REG_D
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bra Z80_common_DEC
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Z80_instr_1D: ; DEC E
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ldx REG_E
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dec REG_E
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bra Z80_common_DEC
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Z80_instr_25: ; DEC H
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ldx REG_H
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dec REG_H
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bra Z80_common_DEC
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Z80_instr_2D: ; DEC L
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ldx REG_L
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dec REG_L
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bra Z80_common_DEC
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Z80_instr_3D: ; DEC A
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Z80_instr_3D: ; DEC A
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ldx REG_A
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dec REG_A
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@@ -330,3 +302,5 @@ Z80_instr_FD_35: ; DEC (IY+d)
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dec
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sta [PTR_DATA],z
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bra Z80_common_DEC
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