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implemented missing Z80 addressing modes

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FeralChild64 committed 2021-01-04 23:14:17 +01:00
1 parent 6e690127e8
commit 8a39aeb8c7
4 files changed
+151 -31
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src/zvm_m65/,aliases_zvm.s
+18 -5
View File
@@ -228,9 +228,22 @@
dez
}
; XXX turn vectors below into macros
!macro Z80_FETCH_VIA_IX_d { ; fetch to .A using IX and displacement
!addr VEC_fetch_via_IX_d = $52
!addr VEC_fetch_via_IY_d = $54
!addr VEC_store_via_IX_d = $56
!addr VEC_store_via_IY_d = $58
jsr Z80_common_fetch_via_IX_d
}
!macro Z80_FETCH_VIA_IY_d { ; fetch to .A using IY and displacement
jsr Z80_common_fetch_via_IY_d
}
!macro Z80_STORE_VIA_IX_d { ; store .X using IX and displacement
jsr Z80_common_store_via_IX_d
}
!macro Z80_STORE_VIA_IY_d { ; store .X using IY and displacement
jsr Z80_common_store_via_IY_d
}
src/zvm_m65/z80_index_regs.s
+107
View File
@@ -0,0 +1,107 @@
;
; Z80 indez register helpers
;
; XXX find a way to optimize them (inline? helper table?)
Z80_common_fetch_via_IX_d:
lda REG_IX+1
sta PTR_DATA+1
lda REG_IX+0
bmi @1
dec PTR_DATA+1
@1:
eor #%10000000
sta PTR_DATA+0
+Z80_FETCH_VIA_PC_INC
tax
lda z80_otable_displacement,x
clc
adc PTR_DATA+0
sta PTR_DATA+0
bcc @2
inc PTR_DATA+1
@2:
lda [PTR_DATA], z
rts
Z80_common_fetch_via_IY_d:
lda REG_IY+1
sta PTR_DATA+1
lda REG_IY+0
bmi @1
dec PTR_DATA+1
@1:
eor #%10000000
sta PTR_DATA+0
+Z80_FETCH_VIA_PC_INC
tax
lda z80_otable_displacement,x
clc
adc PTR_DATA+0
sta PTR_DATA+0
bcc @2
inc PTR_DATA+1
@2:
lda [PTR_DATA], z
rts
Z80_common_store_via_IX_d:
lda REG_IX+1
sta PTR_DATA+1
lda REG_IX+0
bmi @1
dec PTR_DATA+1
@1:
eor #%10000000
sta PTR_DATA+0
+Z80_FETCH_VIA_PC_INC
tax
lda z80_otable_displacement,x
clc
adc PTR_DATA+0
sta PTR_DATA+0
bcc @2
inc PTR_DATA+1
@2:
txa
sta [PTR_DATA], z
rts
Z80_common_store_via_IY_d:
lda REG_IY+1
sta PTR_DATA+1
lda REG_IY+0
bmi @1
dec PTR_DATA+1
@1:
eor #%10000000
sta PTR_DATA+0
+Z80_FETCH_VIA_PC_INC
tax
lda z80_otable_displacement,x
clc
adc PTR_DATA+0
sta PTR_DATA+0
bcc @2
inc PTR_DATA+1
@2:
txa
sta [PTR_DATA], z
rts
src/zvm_m65/z80_instr_load_8bit.s
+6 -6
View File
@@ -193,7 +193,7 @@ Z80_instr_3A: ;
jmp ZVM_next
!macro Z80_LD_REGn_VIA_IX_d .REGn {
jsr (VEC_fetch_via_IX_d)
+Z80_FETCH_VIA_IX_d
sta .REGn
jmp ZVM_next
}
@@ -207,7 +207,7 @@ Z80_instr_DD_6E: +Z80_LD_REGn_VIA_IX_d REG_L ;
Z80_instr_DD_7E: +Z80_LD_REGn_VIA_IX_d REG_A ; LD A,(IX+d)
!macro Z80_LD_REGn_VIA_IY_d .REGn {
jsr (VEC_fetch_via_IY_d)
+Z80_FETCH_VIA_IX_d
sta .REGn
jmp ZVM_next
}
@@ -221,8 +221,8 @@ Z80_instr_FD_6E: +Z80_LD_REGn_VIA_IY_d REG_L ;
Z80_instr_FD_7E: +Z80_LD_REGn_VIA_IY_d REG_A ; LD A,(IY+d)
!macro Z80_LD_VIA_IX_d_REG_n .REGn {
lda .REGn
jsr (VEC_store_via_IX_d)
ldx .REGn
+Z80_STORE_VIA_IX_d
jmp ZVM_next
}
@@ -235,8 +235,8 @@ Z80_instr_DD_75: +Z80_LD_VIA_IX_d_REG_n REG_L ;
Z80_instr_DD_77: +Z80_LD_VIA_IX_d_REG_n REG_A ; LD (IX+d),A
!macro Z80_LD_VIA_IY_d_REG_n .REGn {
lda .REGn
jsr (VEC_store_via_IY_d)
ldx .REGn
+Z80_STORE_VIA_IY_d
jmp ZVM_next
}
src/zvm_m65/z80_instr_math_8bit.s
+20 -20
View File
@@ -41,23 +41,23 @@
}
!macro Z80_ADD_VIA_IX_d {
jsr (VEC_fetch_via_IX_d)
+Z80_FETCH_VIA_IX_d
bra Z80_common_add
}
!macro Z80_ADC_VIA_IX_d {
jsr (VEC_fetch_via_IX_d)
+Z80_FETCH_VIA_IX_d
bbs0 REG_F,Z80_common_adc
jmp Z80_common_add
}
!macro Z80_ADD_VIA_IY_d {
jsr (VEC_fetch_via_IY_d)
+Z80_FETCH_VIA_IY_d
bra Z80_common_add
}
!macro Z80_ADC_VIA_IY_d {
jsr (VEC_fetch_via_IY_d)
+Z80_FETCH_VIA_IY_d
bbs0 REG_F,Z80_common_adc
jmp Z80_common_add
}
@@ -200,23 +200,23 @@ Z80_common_adc:
}
!macro Z80_SUB_VIA_IX_d {
jsr (VEC_fetch_via_IX_d)
+Z80_FETCH_VIA_IX_d
bra Z80_common_sub
}
!macro Z80_SBC_VIA_IX_d {
jsr (VEC_fetch_via_IX_d)
+Z80_FETCH_VIA_IX_d
bbs0 REG_F,Z80_common_sbc
jmp Z80_common_sub
}
!macro Z80_SUB_VIA_IY_d {
jsr (VEC_fetch_via_IY_d)
+Z80_FETCH_VIA_IY_d
bra Z80_common_sub
}
!macro Z80_SBC_VIA_IY_d {
jsr (VEC_fetch_via_IY_d)
+Z80_FETCH_VIA_IY_d
bbs0 REG_F,Z80_common_sbc
jmp Z80_common_sub
}
@@ -341,12 +341,12 @@ Z80_common_sbc:
}
!macro Z80_CP_VIA_IX_d {
jsr (VEC_fetch_via_IX_d)
+Z80_FETCH_VIA_IX_d
bra Z80_common_cp
}
!macro Z80_CP_VIA_IY_d {
jsr (VEC_fetch_via_IY_d)
+Z80_FETCH_VIA_IY_d
bra Z80_common_cp
}
@@ -436,12 +436,12 @@ Z80_common_cp:
}
!macro Z80_AND_VIA_IX_d {
jsr (VEC_fetch_via_IX_d)
+Z80_FETCH_VIA_IX_d
+Z80_AND_common
}
!macro Z80_AND_VIA_IY_d {
jsr (VEC_fetch_via_IY_d)
+Z80_FETCH_VIA_IY_d
+Z80_AND_common
}
@@ -496,12 +496,12 @@ Z80_instr_FD_A6: +Z80_AND_VIA_IY_d ;
}
!macro Z80_OR_VIA_IX_d {
jsr (VEC_fetch_via_IX_d)
+Z80_FETCH_VIA_IX_d
+Z80_OR_common
}
!macro Z80_OR_VIA_IY_d {
jsr (VEC_fetch_via_IY_d)
+Z80_FETCH_VIA_IY_d
+Z80_OR_common
}
@@ -553,12 +553,12 @@ Z80_instr_FD_B6: +Z80_OR_VIA_IY_d ;
}
!macro Z80_XOR_VIA_IX_d {
jsr (VEC_fetch_via_IX_d)
+Z80_FETCH_VIA_IX_d
+Z80_XOR_common
}
!macro Z80_XOR_VIA_IY_d {
jsr (VEC_fetch_via_IY_d)
+Z80_FETCH_VIA_IY_d
+Z80_XOR_common
}
@@ -620,7 +620,7 @@ Z80_instr_34: ; INC (HL)
Z80_instr_DD_34: ; INC (IX+d)
jsr (VEC_fetch_via_IX_d)
+Z80_FETCH_VIA_IX_d
tax
inc
sta [PTR_DATA],z
@@ -628,7 +628,7 @@ Z80_instr_DD_34: ; INC (IX+d)
Z80_instr_FD_34: ; INC (IY+d)
jsr (VEC_fetch_via_IY_d)
+Z80_FETCH_VIA_IY_d
tax
inc
sta [PTR_DATA],z
@@ -676,7 +676,7 @@ Z80_instr_35: ; DEC (HL)
Z80_instr_DD_35: ; DEC (IX+d)
jsr (VEC_fetch_via_IX_d)
+Z80_FETCH_VIA_IX_d
tax
dec
sta [PTR_DATA],z
@@ -684,7 +684,7 @@ Z80_instr_DD_35: ; DEC (IX+d)
Z80_instr_FD_35: ; DEC (IY+d)
jsr (VEC_fetch_via_IY_d)
+Z80_FETCH_VIA_IY_d
tax
dec
sta [PTR_DATA],z