small Z80 additions
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@@ -39,7 +39,8 @@ ZVM_next: ; fetch and execute next opcode
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; CPU main loop
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jsr (VEC_fetch_opcode)
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inc REG_R06
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jsr (VEC_fetch_value)
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asl
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bcs @1
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@@ -86,12 +87,6 @@ ZVM_next: ; fetch and execute next opcode
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@@ -111,18 +106,14 @@ Z80_instr_DD_CB: ; #DDCB
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Z80_instr_FD_CB: ; #FDCB
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Z80_instr_01: ; LD BC,nn
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Z80_instr_02: ; LD (BC),A
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Z80_instr_07: ; RLCA
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Z80_instr_09: ; ADD HL,BC
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Z80_instr_0A: ; LD A,(BC)
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Z80_instr_0F: ; RRCA
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Z80_instr_10: ; DJNZ e
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Z80_instr_11: ; LD DE,nn
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Z80_instr_12: ; LD (DE),A
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Z80_instr_17: ; RLA
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Z80_instr_18: ; JR e
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Z80_instr_19: ; ADD HL,DE
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Z80_instr_1A: ; LD A,(DE)
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Z80_instr_1F: ; RRA
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Z80_instr_1A: ; LD A,(DE)
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Z80_instr_20: ; JR NZ,e
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Z80_instr_21: ; LD HL,nn
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Z80_instr_22: ; LD (nn),HL
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