updated pre-built binaries,. explained similarities
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@@ -22,18 +22,18 @@ reset_entry:
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jmp (ICART_COLD_START)
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*
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; Initialising IO is obviously required. Also indicated by c64 prg p269.
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jsr IOINIT
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jsr JIOINIT
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; Setting up the screen and testing ram is obviously required
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; also affirmed by p269 of c64 prg
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jsr RAMTAS ; called RANTAM on Codebase64 wiki
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jsr JRAMTAS ; called RANTAM on Codebase64 wiki
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; Resetting IO vectors is obviously required, if we want interrupts to run
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; also affirmed by c64 prg p269
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jsr RESTOR
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jsr JRESTOR
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;; "Compute's Mapping the 64" p236
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jsr CINT
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jsr JCINT
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; What do we do when finished? A C64 jumps into the BASIC ROM
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cli ; Allow interrupts to happen
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@@ -0,0 +1,3 @@
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$DD00 + AND #$DF
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Instruction and a half (well known hardware register address) - not copyrightable.
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@@ -0,0 +1,5 @@
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$DD00 + AND #$DF + STA $DD00 + RTS
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$DD00 is a hardware register, where one typically set/unset/read individual bits.
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Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
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Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.
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@@ -0,0 +1,3 @@
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JSR $EE06 + LDA (argument does not match)
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Instruction and a half - not copyrightable.
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@@ -0,0 +1 @@
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This is a part of Kernal jumptable - series of jumps, sometimes to the well known addreses (or through documented vectors). No business logic, part of the Kernal API itself (has to be as it is to maintain compatibility) - not copyrightable.
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@@ -0,0 +1 @@
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This is a part of Kernal jumptable - series of jumps, sometimes to the well known addreses (or through documented vectors). No business logic, part of the Kernal API itself (has to be as it is to maintain compatibility) - not copyrightable.
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+1
-1
@@ -1,4 +1,4 @@
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RTS (from previous routine) + a list of vectors to be copied starting from $0314
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RTS (from previous routine) + a list of vectors to be copied starting from $0314 + LDA #$00
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Values of the vectors are already present in many autostart software - as it often overrides them,
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sometimes changing one to trigger autostart (one of the possible techniques). We have to use the same
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@@ -1 +1 @@
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This is a part of Kernal jumptable - series of jumps, sometimes to the well known addreses (or through documented vectors). No business logic, part of the Kernal API itself - not copyrightable.
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This is a part of Kernal jumptable - series of jumps, sometimes to the well known addreses (or through documented vectors). No business logic, part of the Kernal API itself (has to be as it is to maintain compatibility) - not copyrightable.
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@@ -0,0 +1,3 @@
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$7F + STA $DC0D
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Instruction (access to a docummented hardware register) and some part - not copyrightable.
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@@ -0,0 +1,3 @@
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TYA + PHA + TSX + LDA $0104,X + AND #$10
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Beginning of IRQ handler - checks whether it is caused by BRK instruction or some other reason. Since IRQ handling for BRK/non-BRK caused interrupts are totally different, there is no other way but to start with such a check. Not creative - not copyrightable.
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@@ -0,0 +1,3 @@
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LDA $9D + BPL (address match)
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Checking a well-known zeropage flag - not creative, not copyrightable.
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@@ -0,0 +1,3 @@
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LDA #$7F + STA $DC00 + LDA $DC01
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Part of keyboard scanning code in UDTIM routine - to get the last row (not even complete code, as there is also some code to set the port directions). This is probably the only sane way to read the rom. Not creative - not copyrightable.
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@@ -0,0 +1,3 @@
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BNE (offset match) + INC $A1 + BNE (offset does not match)
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Part of the routine to increment a well-known 24-bit counter. There are not many ways to do this in a sane way, some similarity is unavoidable, 2 instructions and a half is not much in this case. Not copyrightable.
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@@ -0,0 +1,5 @@
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$DD + ORA #$08 + STA $DD00
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$DD00 is a hardware register, where one typically set/unset/read individual bits.
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Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
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Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.
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@@ -0,0 +1,5 @@
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$DD + RTS + LDA $DD00 + ORA #$10
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$DD00 is a hardware register, where one typically set/unset/read individual bits.
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Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
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Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.
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@@ -0,0 +1,5 @@
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$DF + STA $DD00 + RTS + LDA $DD00 + ORA (argument does not match)
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$DD00 is a hardware register, where one typically set/unset/read individual bits.
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Having a set of trivial helper subroutines to set/clear individual bits (or groups of bits) is an obvious solution (thus not copyrightable), some similarities are unevitable.
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Besides, in this case (since the similarity does not even cover a single subroutine from start to end) it is clear that the similar code actually performs slightly different actions.
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@@ -0,0 +1,3 @@
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$EE + LDA $DD00
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Instruction (access to a well known hardware register address) and a half - not copyrightable.
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@@ -0,0 +1 @@
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This is a part of Kernal jumptable - series of jumps, sometimes to the well known addreses (or through documented vectors). No business logic, part of the Kernal API itself (has to be as it is to maintain compatibility) - not copyrightable.
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@@ -0,0 +1,3 @@
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$FF + CLI + JMP ($A000)
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Part of the address, reenabling interrupts, jump through a documented vector - part of the initialization/reset sequence. Not creative - not copyrightable.
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