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more Z80 work

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FeralChild64 authored and FeralChild64 committed 2021-01-26 00:03:07 +01:00
1 parent 93d6aaaea2
commit a71ebe4968
3 files changed
+412 -70
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src/zvm_m65/z80_instr_io.s
+28
View File
@@ -3,6 +3,8 @@
; Z80 input/output instructions
;
; XXX ZVM_store_IO should go to next instruction
Z80_instr_DB: ; IN A,(n)
@@ -29,6 +31,20 @@ Z80_instr_DB: ;
jmp ZVM_next
}
!macro Z80_IN_NULL {
lda REG_C
sta ADDR_IO+0
lda REG_B
sta ADDR_IO+1
jsr ZVM_fetch_IO
tax
lda REG_F
and #($FF - Z80_SF - Z80_ZF - Z80_HF - Z80_PF - Z80_NF - Z80_XF - Z80_YF)
ora z80_ftable_IN_OR_XOR, x
sta REG_F
jmp ZVM_next
}
Z80_instr_ED_40: +Z80_IN_REGn REG_B ; IN B,(C)
Z80_instr_ED_48: +Z80_IN_REGn REG_C ; IN C,(C)
Z80_instr_ED_50: +Z80_IN_REGn REG_D ; IN D,(C)
@@ -36,6 +52,7 @@ Z80_instr_ED_58: +Z80_IN_REGn REG_E ;
Z80_instr_ED_60: +Z80_IN_REGn REG_H ; IN H,(C)
Z80_instr_ED_68: +Z80_IN_REGn REG_L ; IN L,(C)
Z80_instr_ED_78: +Z80_IN_REGn REG_A ; IN A,(C)
Z80_illeg_ED_70: +Z80_IN_NULL ; IN (C)
Z80_instr_D3: ; OUT (n),A
@@ -74,8 +91,19 @@ Z80_instr_ED_49: ;
jmp ZVM_next
}
!macro Z80_OUT_NULL {
lda REG_C
sta ADDR_IO+0
lda REG_B
sta ADDR_IO+1
lda #$00
jsr ZVM_store_IO
jmp ZVM_next
}
Z80_instr_ED_51: +Z80_OUT_REGn REG_D ; OUT (C),D
Z80_instr_ED_59: +Z80_OUT_REGn REG_E ; OUT (C),E
Z80_instr_ED_61: +Z80_OUT_REGn REG_H ; OUT (C),H
Z80_instr_ED_69: +Z80_OUT_REGn REG_L ; OUT (C),L
Z80_instr_ED_79: +Z80_OUT_REGn REG_A ; OUT (C),A
Z80_illeg_ED_71: +Z80_OUT_NULL ; OUT (C),0
src/zvm_m65/z80_instr_rotate_shift.s
+376 -2
View File
@@ -190,6 +190,45 @@ Z80_instr_1F: ; RRA
jmp ZVM_next
}
!macro Z80_RLC_VIA_IXY_d {
lda [PTR_IXY_d] ,z
tax
rol
txa
rol
sta [PTR_IXY_d],z
tax
lda z80_ftable_IN_OR_XOR, x
sta REG_F
+bcc ZVM_next
+Z80_PUT_1_CF
jmp ZVM_next
}
!macro Z80_RLC_VIA_IXY_d_REGn .REGn {
lda [PTR_IXY_d] ,z
tax
rol
txa
rol
sta [PTR_IXY_d],z
sta .REGn
tax
lda z80_ftable_IN_OR_XOR, x
sta REG_F
+bcc ZVM_next
+Z80_PUT_1_CF
jmp ZVM_next
}
Z80_instr_CB_00: +Z80_RLC_REGn REG_B ; RLC B
Z80_instr_CB_01: +Z80_RLC_REGn REG_C ; RLC C
Z80_instr_CB_02: +Z80_RLC_REGn REG_D ; RLC D
@@ -198,6 +237,15 @@ Z80_instr_CB_04: +Z80_RLC_REGn REG_H ;
Z80_instr_CB_05: +Z80_RLC_REGn REG_L ; RLC L
Z80_instr_CB_07: +Z80_RLC_REGn REG_A ; RLC A
Z80_instr_CB_06: +Z80_RLC_VIA_HL ; RLC (HL)
Z80_instr_xDCB_06: +Z80_RLC_VIA_IXY_d ; RLC (IXY+d)
Z80_illeg_xDCB_00: +Z80_RLC_VIA_IXY_d_REGn REG_B ; RLC (IXY+d),B
Z80_illeg_xDCB_01: +Z80_RLC_VIA_IXY_d_REGn REG_C ; RLC (IXY+d),C
Z80_illeg_xDCB_02: +Z80_RLC_VIA_IXY_d_REGn REG_D ; RLC (IXY+d),D
Z80_illeg_xDCB_03: +Z80_RLC_VIA_IXY_d_REGn REG_E ; RLC (IXY+d),E
Z80_illeg_xDCB_04: +Z80_RLC_VIA_IXY_d_REGn REG_H ; RLC (IXY+d),H
Z80_illeg_xDCB_05: +Z80_RLC_VIA_IXY_d_REGn REG_L ; RLC (IXY+d),L
Z80_illeg_xDCB_07: +Z80_RLC_VIA_IXY_d_REGn REG_A ; RLC (IXY+d),A
!macro Z80_RRC_REGn .REGn {
@@ -234,6 +282,45 @@ Z80_instr_CB_06: +Z80_RLC_VIA_HL ;
jmp ZVM_next
}
!macro Z80_RRC_VIA_IXY_d {
lda [PTR_IXY_d] ,z
tax
ror
txa
ror
sta [PTR_IXY_d],z
tax
lda z80_ftable_IN_OR_XOR, x
sta REG_F
+bcc ZVM_next
+Z80_PUT_1_CF
jmp ZVM_next
}
!macro Z80_RRC_VIA_IXY_d_REGn .REGn {
lda [PTR_IXY_d] ,z
tax
ror
txa
ror
sta [PTR_IXY_d],z
sta .REGn
tax
lda z80_ftable_IN_OR_XOR, x
sta REG_F
+bcc ZVM_next
+Z80_PUT_1_CF
jmp ZVM_next
}
Z80_instr_CB_08: +Z80_RRC_REGn REG_B ; RRC B
Z80_instr_CB_09: +Z80_RRC_REGn REG_C ; RRC C
Z80_instr_CB_0A: +Z80_RRC_REGn REG_D ; RRC D
@@ -242,6 +329,15 @@ Z80_instr_CB_0C: +Z80_RRC_REGn REG_H ;
Z80_instr_CB_0D: +Z80_RRC_REGn REG_L ; RRC L
Z80_instr_CB_0F: +Z80_RRC_REGn REG_A ; RRC A
Z80_instr_CB_0E: +Z80_RRC_VIA_HL ; RRC (HL)
Z80_instr_xDCB_0E: +Z80_RRC_VIA_IXY_d ; RRC (IXY+d)
Z80_illeg_xDCB_08: +Z80_RRC_VIA_IXY_d_REGn REG_B ; RRC (IXY+d),B
Z80_illeg_xDCB_09: +Z80_RRC_VIA_IXY_d_REGn REG_C ; RRC (IXY+d),C
Z80_illeg_xDCB_0A: +Z80_RRC_VIA_IXY_d_REGn REG_D ; RRC (IXY+d),D
Z80_illeg_xDCB_0B: +Z80_RRC_VIA_IXY_d_REGn REG_E ; RRC (IXY+d),E
Z80_illeg_xDCB_0C: +Z80_RRC_VIA_IXY_d_REGn REG_H ; RRC (IXY+d),H
Z80_illeg_xDCB_0D: +Z80_RRC_VIA_IXY_d_REGn REG_L ; RRC (IXY+d),L
Z80_illeg_xDCB_0F: +Z80_RRC_VIA_IXY_d_REGn REG_A ; RRC (IXY+d),A
!macro Z80_RL_REGn .REGn {
@@ -278,6 +374,45 @@ Z80_instr_CB_0E: +Z80_RRC_VIA_HL ;
jmp ZVM_next
}
!macro Z80_RL_VIA_IXY_d {
lda [PTR_IXY_d] ,z
clc
bbr0 REG_F, @1
sec
@1:
rol
sta [PTR_IXY_d],z
tax
lda z80_ftable_IN_OR_XOR, x
sta REG_F
+bcc ZVM_next
+Z80_PUT_1_CF
jmp ZVM_next
}
!macro Z80_RL_VIA_IXY_d_REGn .REGn {
lda [PTR_IXY_d] ,z
clc
bbr0 REG_F, @1
sec
@1:
rol
sta [PTR_IXY_d],z
sta .REGn
tax
lda z80_ftable_IN_OR_XOR, x
sta REG_F
+bcc ZVM_next
+Z80_PUT_1_CF
jmp ZVM_next
}
Z80_instr_CB_10: +Z80_RL_REGn REG_B ; RL B
Z80_instr_CB_11: +Z80_RL_REGn REG_C ; RL C
Z80_instr_CB_12: +Z80_RL_REGn REG_D ; RL D
@@ -286,6 +421,15 @@ Z80_instr_CB_14: +Z80_RL_REGn REG_H ;
Z80_instr_CB_15: +Z80_RL_REGn REG_L ; RL L
Z80_instr_CB_17: +Z80_RL_REGn REG_A ; RL A
Z80_instr_CB_16: +Z80_RL_VIA_HL ; RL (HL)
Z80_instr_xDCB_16: +Z80_RL_VIA_IXY_d ; RL (IXY+d)
Z80_illeg_xDCB_10: +Z80_RL_VIA_IXY_d_REGn REG_B ; RL (IXY+d),B
Z80_illeg_xDCB_11: +Z80_RL_VIA_IXY_d_REGn REG_C ; RL (IXY+d),C
Z80_illeg_xDCB_12: +Z80_RL_VIA_IXY_d_REGn REG_D ; RL (IXY+d),D
Z80_illeg_xDCB_13: +Z80_RL_VIA_IXY_d_REGn REG_E ; RL (IXY+d),E
Z80_illeg_xDCB_14: +Z80_RL_VIA_IXY_d_REGn REG_H ; RL (IXY+d),H
Z80_illeg_xDCB_15: +Z80_RL_VIA_IXY_d_REGn REG_L ; RL (IXY+d),L
Z80_illeg_xDCB_17: +Z80_RL_VIA_IXY_d_REGn REG_A ; RL (IXY+d),A
!macro Z80_RR_REGn .REGn {
@@ -322,6 +466,45 @@ Z80_instr_CB_16: +Z80_RL_VIA_HL ;
jmp ZVM_next
}
!macro Z80_RR_VIA_IXY_d {
lda [PTR_IXY_d] ,z
clc
bbr0 REG_F, @1
sec
@1:
ror
sta [PTR_IXY_d],z
tax
lda z80_ftable_IN_OR_XOR, x
sta REG_F
+bcc ZVM_next
+Z80_PUT_1_CF
jmp ZVM_next
}
!macro Z80_RR_VIA_IXY_d_REGn .REGn {
lda [PTR_IXY_d] ,z
clc
bbr0 REG_F, @1
sec
@1:
ror
sta [PTR_IXY_d],z
sta .REGn
tax
lda z80_ftable_IN_OR_XOR, x
sta REG_F
+bcc ZVM_next
+Z80_PUT_1_CF
jmp ZVM_next
}
Z80_instr_CB_18: +Z80_RR_REGn REG_B ; RR B
Z80_instr_CB_19: +Z80_RR_REGn REG_C ; RR C
Z80_instr_CB_1A: +Z80_RR_REGn REG_D ; RR D
@@ -330,6 +513,15 @@ Z80_instr_CB_1C: +Z80_RR_REGn REG_H ;
Z80_instr_CB_1D: +Z80_RR_REGn REG_L ; RR L
Z80_instr_CB_1F: +Z80_RR_REGn REG_A ; RR A
Z80_instr_CB_1E: +Z80_RR_VIA_HL ; RR (HL)
Z80_instr_xDCB_1E: +Z80_RR_VIA_IXY_d ; RR (IXY+d)
Z80_illeg_xDCB_18: +Z80_RR_VIA_IXY_d_REGn REG_B ; RR (IXY+d),B
Z80_illeg_xDCB_19: +Z80_RR_VIA_IXY_d_REGn REG_C ; RR (IXY+d),C
Z80_illeg_xDCB_1A: +Z80_RR_VIA_IXY_d_REGn REG_D ; RR (IXY+d),D
Z80_illeg_xDCB_1B: +Z80_RR_VIA_IXY_d_REGn REG_E ; RR (IXY+d),E
Z80_illeg_xDCB_1C: +Z80_RR_VIA_IXY_d_REGn REG_H ; RR (IXY+d),H
Z80_illeg_xDCB_1D: +Z80_RR_VIA_IXY_d_REGn REG_L ; RR (IXY+d),L
Z80_illeg_xDCB_1F: +Z80_RR_VIA_IXY_d_REGn REG_A ; RR (IXY+d),A
; XXX SLA/SLL (and possibly rotations) can be made slightly faster with dedicated tables (omit carry flag calculation)
@@ -345,7 +537,7 @@ Z80_instr_CB_1E: +Z80_RR_VIA_HL ;
jmp ZVM_next
}
!macro Z80_SLA_VIA {
!macro Z80_SLA_VIA_HL {
jsr (VEC_fetch_via_HL)
asl
@@ -359,6 +551,35 @@ Z80_instr_CB_1E: +Z80_RR_VIA_HL ;
jmp ZVM_next
}
!macro Z80_SLA_VIA_IXY_d {
lda [PTR_IXY_d] ,z
asl
sta [PTR_IXY_d],z
tax
lda z80_ftable_IN_OR_XOR, x
sta REG_F
+bcc ZVM_next
+Z80_PUT_1_CF
jmp ZVM_next
}
!macro Z80_SLA_VIA_IXY_d_REGn .REGn {
lda [PTR_IXY_d] ,z
asl
sta [PTR_IXY_d],z
sta .REGn
tax
lda z80_ftable_IN_OR_XOR, x
sta REG_F
+bcc ZVM_next
+Z80_PUT_1_CF
jmp ZVM_next
}
Z80_instr_CB_20: +Z80_SLA_REGn REG_B ; SLA B
Z80_instr_CB_21: +Z80_SLA_REGn REG_C ; SLA C
Z80_instr_CB_22: +Z80_SLA_REGn REG_D ; SLA D
@@ -366,7 +587,16 @@ Z80_instr_CB_23: +Z80_SLA_REGn REG_E ;
Z80_instr_CB_24: +Z80_SLA_REGn REG_H ; SLA H
Z80_instr_CB_25: +Z80_SLA_REGn REG_L ; SLA L
Z80_instr_CB_27: +Z80_SLA_REGn REG_A ; SLA A
Z80_instr_CB_26: +Z80_SLA_VIA ; SLA (HL)
Z80_instr_CB_26: +Z80_SLA_VIA_HL ; SLA (HL)
Z80_instr_xDCB_26: +Z80_SLA_VIA_IXY_d ; SLA (IXY+d)
Z80_illeg_xDCB_20: +Z80_SLA_VIA_IXY_d_REGn REG_B ; SLA (IXY+d),B
Z80_illeg_xDCB_21: +Z80_SLA_VIA_IXY_d_REGn REG_C ; SLA (IXY+d),C
Z80_illeg_xDCB_22: +Z80_SLA_VIA_IXY_d_REGn REG_D ; SLA (IXY+d),D
Z80_illeg_xDCB_23: +Z80_SLA_VIA_IXY_d_REGn REG_E ; SLA (IXY+d),E
Z80_illeg_xDCB_24: +Z80_SLA_VIA_IXY_d_REGn REG_H ; SLA (IXY+d),H
Z80_illeg_xDCB_25: +Z80_SLA_VIA_IXY_d_REGn REG_L ; SLA (IXY+d),L
Z80_illeg_xDCB_27: +Z80_SLA_VIA_IXY_d_REGn REG_A ; SLA (IXY+d),A
!macro Z80_SLL_REGn .REGn {
@@ -381,6 +611,52 @@ Z80_instr_CB_26: +Z80_SLA_VIA ;
jmp ZVM_next
}
!macro Z80_SLL_VIA_HL {
jsr (VEC_fetch_via_HL)
sec
rol
sta [PTR_DATA],z
tax
lda z80_ftable_IN_OR_XOR, x
sta REG_F
+bcc ZVM_next
+Z80_PUT_1_CF
jmp ZVM_next
}
!macro Z80_SLL_VIA_IXY_d {
lda [PTR_IXY_d] ,z
sec
rol
sta [PTR_IXY_d],z
tax
lda z80_ftable_IN_OR_XOR, x
sta REG_F
+bcc ZVM_next
+Z80_PUT_1_CF
jmp ZVM_next
}
!macro Z80_SLL_VIA_IXY_d_REGn .REGn {
lda [PTR_IXY_d] ,z
sec
rol
sta [PTR_IXY_d],z
sta .REGn
tax
lda z80_ftable_IN_OR_XOR, x
sta REG_F
+bcc ZVM_next
+Z80_PUT_1_CF
jmp ZVM_next
}
Z80_illeg_CB_30: +Z80_SLL_REGn REG_B ; SLL B
Z80_illeg_CB_31: +Z80_SLL_REGn REG_C ; SLL C
Z80_illeg_CB_32: +Z80_SLL_REGn REG_D ; SLL D
@@ -388,6 +664,16 @@ Z80_illeg_CB_33: +Z80_SLL_REGn REG_E ;
Z80_illeg_CB_34: +Z80_SLL_REGn REG_H ; SLL H
Z80_illeg_CB_35: +Z80_SLL_REGn REG_L ; SLL L
Z80_illeg_CB_37: +Z80_SLL_REGn REG_A ; SLL A
Z80_illeg_CB_36: +Z80_SLL_VIA_HL ; SLL (HL)
Z80_illeg_xDCB_36: +Z80_SLL_VIA_IXY_d ; SLL (IXY+d)
Z80_illeg_xDCB_30: +Z80_SLL_VIA_IXY_d_REGn REG_B ; SLL (IXY+d),B
Z80_illeg_xDCB_31: +Z80_SLL_VIA_IXY_d_REGn REG_C ; SLL (IXY+d),C
Z80_illeg_xDCB_32: +Z80_SLL_VIA_IXY_d_REGn REG_D ; SLL (IXY+d),D
Z80_illeg_xDCB_33: +Z80_SLL_VIA_IXY_d_REGn REG_E ; SLL (IXY+d),E
Z80_illeg_xDCB_34: +Z80_SLL_VIA_IXY_d_REGn REG_H ; SLL (IXY+d),H
Z80_illeg_xDCB_35: +Z80_SLL_VIA_IXY_d_REGn REG_L ; SLL (IXY+d),L
Z80_illeg_xDCB_37: +Z80_SLL_VIA_IXY_d_REGn REG_A ; SLL (IXY+d),A
!macro Z80_SRL_REGn .REGn {
@@ -417,6 +703,37 @@ Z80_illeg_CB_37: +Z80_SLL_REGn REG_A ;
jmp ZVM_next
}
!macro Z80_SRL_VIA_IXY_d {
lda [PTR_IXY_d] ,z
clc
ror
sta [PTR_IXY_d],z
tax
lda z80_ftable_IN_OR_XOR, x
sta REG_F
+bcc ZVM_next
+Z80_PUT_1_CF
jmp ZVM_next
}
!macro Z80_SRL_VIA_IXY_d_REGn .REGn {
lda [PTR_IXY_d] ,z
clc
ror
sta [PTR_IXY_d],z
sta .REGn
tax
lda z80_ftable_IN_OR_XOR, x
sta REG_F
+bcc ZVM_next
+Z80_PUT_1_CF
jmp ZVM_next
}
Z80_instr_CB_38: +Z80_SRL_REGn REG_B ; SRL B
Z80_instr_CB_39: +Z80_SRL_REGn REG_C ; SRL C
Z80_instr_CB_3A: +Z80_SRL_REGn REG_D ; SRL D
@@ -425,6 +742,15 @@ Z80_instr_CB_3C: +Z80_SRL_REGn REG_H ;
Z80_instr_CB_3D: +Z80_SRL_REGn REG_L ; SRL L
Z80_instr_CB_3F: +Z80_SRL_REGn REG_A ; SRL A
Z80_instr_CB_3E: +Z80_SRL_VIA_HL ; SRL (HL)
Z80_instr_xDCB_3E: +Z80_SRL_VIA_IXY_d ; SRL (IXY+d)
Z80_illeg_xDCB_38: +Z80_SRL_VIA_IXY_d_REGn REG_B ; SLR (IXY+d),B
Z80_illeg_xDCB_39: +Z80_SRL_VIA_IXY_d_REGn REG_C ; SLR (IXY+d),C
Z80_illeg_xDCB_3A: +Z80_SRL_VIA_IXY_d_REGn REG_D ; SLR (IXY+d),D
Z80_illeg_xDCB_3B: +Z80_SRL_VIA_IXY_d_REGn REG_E ; SLR (IXY+d),E
Z80_illeg_xDCB_3C: +Z80_SRL_VIA_IXY_d_REGn REG_H ; SLR (IXY+d),H
Z80_illeg_xDCB_3D: +Z80_SRL_VIA_IXY_d_REGn REG_L ; SLR (IXY+d),L
Z80_illeg_xDCB_3F: +Z80_SRL_VIA_IXY_d_REGn REG_A ; SLR (IXY+d),A
!macro Z80_SRA_REGn .REGn {
@@ -461,6 +787,45 @@ Z80_instr_CB_3E: +Z80_SRL_VIA_HL ;
jmp ZVM_next
}
!macro Z80_SRA_VIA_IXY_d {
lda [PTR_IXY_d] ,z
tax
ror
txa
ror
sta [PTR_IXY_d],z
tax
lda z80_ftable_IN_OR_XOR, x
sta REG_F
+bcc ZVM_next
+Z80_PUT_1_CF
jmp ZVM_next
}
!macro Z80_SRA_VIA_IXY_d_REGn .REGn {
lda [PTR_IXY_d] ,z
tax
ror
txa
ror
sta [PTR_IXY_d],z
sta .REGn
tax
lda z80_ftable_IN_OR_XOR, x
sta REG_F
+bcc ZVM_next
+Z80_PUT_1_CF
jmp ZVM_next
}
Z80_instr_CB_28: +Z80_SRA_REGn REG_B ; SRA B
Z80_instr_CB_29: +Z80_SRA_REGn REG_C ; SRA C
Z80_instr_CB_2A: +Z80_SRA_REGn REG_D ; SRA D
@@ -469,3 +834,12 @@ Z80_instr_CB_2C: +Z80_SRA_REGn REG_H ;
Z80_instr_CB_2D: +Z80_SRA_REGn REG_L ; SRA L
Z80_instr_CB_2F: +Z80_SRA_REGn REG_A ; SRA A
Z80_instr_CB_2E: +Z80_SRA_VIA_HL ; SRA (HL)
Z80_instr_xDCB_2E: +Z80_SRA_VIA_IXY_d ; SRA (IXY+d)
Z80_illeg_xDCB_28: +Z80_SRA_VIA_IXY_d_REGn REG_B ; SRA (IXY+d),B
Z80_illeg_xDCB_29: +Z80_SRA_VIA_IXY_d_REGn REG_C ; SRA (IXY+d),C
Z80_illeg_xDCB_2A: +Z80_SRA_VIA_IXY_d_REGn REG_D ; SRA (IXY+d),D
Z80_illeg_xDCB_2B: +Z80_SRA_VIA_IXY_d_REGn REG_E ; SRA (IXY+d),E
Z80_illeg_xDCB_2C: +Z80_SRA_VIA_IXY_d_REGn REG_H ; SRA (IXY+d),H
Z80_illeg_xDCB_2D: +Z80_SRA_VIA_IXY_d_REGn REG_L ; SRA (IXY+d),L
Z80_illeg_xDCB_2F: +Z80_SRA_VIA_IXY_d_REGn REG_A ; SRA (IXY+d),A
src/zvm_m65/zvm_core.s
+8 -68
View File
@@ -188,6 +188,8 @@ Z80_instr_FD: +ZVM_DISPATCH Z80_vectab_FD_0, Z80_vectab_FD_1 ;
@@ -202,83 +204,21 @@ Z80_instr_ED_A1: ; CPI
Z80_instr_ED_A9: ; CPD
Z80_instr_ED_B1: ; CPIR
Z80_instr_ED_B9: ; CPDR
Z80_instr_xDCB_06: ; RLC (IXY+d)
Z80_instr_xDCB_0E: ; RRC (IXY+d)
Z80_instr_xDCB_16: ; RL (IXY+d)
Z80_instr_xDCB_1E: ; RR (IXY+d)
Z80_instr_xDCB_26: ; SLA (IXY+d)
Z80_instr_xDCB_2E: ; SRA (IXY+d)
Z80_instr_xDCB_3E: ; SRL (IXY+d)
Z80_illeg_CB_36: ; SLL (HL)
Z80_illeg_ED_70: ; IN F,(C)
Z80_illeg_ED_71: ; OUT (C),0
Z80_illeg_xDCB_00: ; RLC (IXY+d),B
Z80_illeg_xDCB_01: ; RLC (IXY+d),C
Z80_illeg_xDCB_02: ; RLC (IXY+d),D
Z80_illeg_xDCB_03: ; RLC (IXY+d),E
Z80_illeg_xDCB_04: ; RLC (IXY+d),H
Z80_illeg_xDCB_05: ; RLC (IXY+d),L
Z80_illeg_xDCB_07: ; RLC (IXY+d),A
Z80_illeg_xDCB_08: ; RRC (IXY+d),B
Z80_illeg_xDCB_09: ; RRC (IXY+d),C
Z80_illeg_xDCB_0A: ; RRC (IXY+d),D
Z80_illeg_xDCB_0B: ; RRC (IXY+d),E
Z80_illeg_xDCB_0C: ; RRC (IXY+d),H
Z80_illeg_xDCB_0D: ; RRC (IXY+d),L
Z80_illeg_xDCB_0F: ; RRC (IXY+d),A
Z80_illeg_xDCB_10: ; RL (IXY+d),B
Z80_illeg_xDCB_11: ; RL (IXY+d),C
Z80_illeg_xDCB_12: ; RL (IXY+d),D
Z80_illeg_xDCB_13: ; RL (IXY+d),E
Z80_illeg_xDCB_14: ; RL (IXY+d),H
Z80_illeg_xDCB_15: ; RL (IXY+d),L
Z80_illeg_xDCB_17: ; RL (IXY+d),A
Z80_illeg_xDCB_18: ; RR (IXY+d),B
Z80_illeg_xDCB_19: ; RR (IXY+d),C
Z80_illeg_xDCB_1A: ; RR (IXY+d),D
Z80_illeg_xDCB_1B: ; RR (IXY+d),E
Z80_illeg_xDCB_1C: ; RR (IXY+d),H
Z80_illeg_xDCB_1D: ; RR (IXY+d),L
Z80_illeg_xDCB_1F: ; RR (IXY+d),A
Z80_illeg_xDCB_20: ; SLA (IXY+d),B
Z80_illeg_xDCB_21: ; SLA (IXY+d),C
Z80_illeg_xDCB_22: ; SLA (IXY+d),D
Z80_illeg_xDCB_23: ; SLA (IXY+d),E
Z80_illeg_xDCB_24: ; SLA (IXY+d),H
Z80_illeg_xDCB_25: ; SLA (IXY+d),L
Z80_illeg_xDCB_27: ; SLA (IXY+d),A
Z80_illeg_xDCB_28: ; SRA (IXY+d),B
Z80_illeg_xDCB_29: ; SRA (IXY+d),C
Z80_illeg_xDCB_2A: ; SRA (IXY+d),D
Z80_illeg_xDCB_2B: ; SRA (IXY+d),E
Z80_illeg_xDCB_2C: ; SRA (IXY+d),H
Z80_illeg_xDCB_2D: ; SRA (IXY+d),L
Z80_illeg_xDCB_2F: ; SRA (IXY+d),A
Z80_illeg_xDCB_30: ; SLL (IXY+d),B
Z80_illeg_xDCB_31: ; SLL (IXY+d),C
Z80_illeg_xDCB_32: ; SLL (IXY+d),D
Z80_illeg_xDCB_33: ; SLL (IXY+d),E
Z80_illeg_xDCB_34: ; SLL (IXY+d),H
Z80_illeg_xDCB_35: ; SLL (IXY+d),L
Z80_illeg_xDCB_36: ; SLL (IXY+d)
Z80_illeg_xDCB_37: ; SLL (IXY+d),A
Z80_illeg_xDCB_38: ; SLR (IXY+d),B
Z80_illeg_xDCB_39: ; SLR (IXY+d),C
Z80_illeg_xDCB_3A: ; SLR (IXY+d),D
Z80_illeg_xDCB_3B: ; SLR (IXY+d),E
Z80_illeg_xDCB_3C: ; SLR (IXY+d),H
Z80_illeg_xDCB_3D: ; SLR (IXY+d),L
Z80_illeg_xDCB_3F: ; SLR (IXY+d),A
jmp ZVM_next ; XXX provide implementation
ZVM_memtest:
; Simple memory test
; XXX this test is temporary
lda #$00
sta PTR_DATA+0
sta PTR_DATA+1