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turned some repeating code into macros

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FeralChild64 authored and FeralChild64 committed 2021-01-26 00:03:07 +01:00
1 parent fb347b6a7b
commit aaedcddba1
2 files changed
+58 -133
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src/zvm_m65/z80_instr_load_16bit.s
+22 -87
View File
@@ -3,98 +3,33 @@
; Z80 data load instructions, 16 bit
;
Z80_instr_C5: ; PUSH BC
lda REG_BC+1
!macro Z80_PUSH_REGnn .REGnn {
lda .REGnn+1
jsr (VEC_store_stack)
lda REG_BC+0
lda .REGnn+0
jsr (VEC_store_stack)
jmp ZVM_next
}
Z80_instr_D5: ; PUSH DE
Z80_instr_C5: +Z80_PUSH_REGnn REG_BC ; PUSH BC
Z80_instr_D5: +Z80_PUSH_REGnn REG_DE ; PUSH DE
Z80_instr_E5: +Z80_PUSH_REGnn REG_HL ; PUSH HL
Z80_instr_F5: +Z80_PUSH_REGnn REG_AF ; PUSH AF
Z80_instr_DD_E5: +Z80_PUSH_REGnn REG_IX ; PUSH IX
Z80_instr_FD_E5: +Z80_PUSH_REGnn REG_IY ; PUSH IY
lda REG_DE+1
jsr (VEC_store_stack)
lda REG_DE+0
jsr (VEC_store_stack)
!macro Z80_POP_REGnn .REGnn {
jsr (VEC_fetch_stack)
sta .REGnn+0
jsr (VEC_fetch_stack)
lda .REGnn+1
jmp ZVM_next
}
Z80_instr_E5: ; PUSH HL
lda REG_HL+1
jsr (VEC_store_stack)
lda REG_HL+0
jsr (VEC_store_stack)
jmp ZVM_next
Z80_instr_F5: ; PUSH AF
lda REG_AF+1
jsr (VEC_store_stack)
lda REG_AF+0
jsr (VEC_store_stack)
jmp ZVM_next
Z80_instr_DD_E5: ; PUSH IX
lda REG_IX+1
jsr (VEC_store_stack)
lda REG_IX+0
jsr (VEC_store_stack)
jmp ZVM_next
Z80_instr_FD_E5: ; PUSH IY
lda REG_IY+1
jsr (VEC_store_stack)
lda REG_IY+0
jsr (VEC_store_stack)
jmp ZVM_next
Z80_instr_C1: ; POP BC
jsr (VEC_fetch_stack)
sta REG_BC+0
jsr (VEC_fetch_stack)
lda REG_BC+1
jmp ZVM_next
Z80_instr_D1: ; POP DE
jsr (VEC_fetch_stack)
sta REG_DE+0
jsr (VEC_fetch_stack)
lda REG_DE+1
jmp ZVM_next
Z80_instr_E1: ; POP HL
jsr (VEC_fetch_stack)
sta REG_HL+0
jsr (VEC_fetch_stack)
lda REG_HL+1
jmp ZVM_next
Z80_instr_F1: ; POP AF
jsr (VEC_fetch_stack)
sta REG_AF+0
jsr (VEC_fetch_stack)
lda REG_AF+1
jmp ZVM_next
Z80_instr_DD_E1: ; POP IX
jsr (VEC_fetch_stack)
sta REG_IX+0
jsr (VEC_fetch_stack)
lda REG_IX+1
jmp ZVM_next
Z80_instr_FD_E1: ; POP IY
jsr (VEC_fetch_stack)
sta REG_IY+0
jsr (VEC_fetch_stack)
lda REG_IY+1
jmp ZVM_next
Z80_instr_C1: +Z80_POP_REGnn REG_BC ; POP BC
Z80_instr_D1: +Z80_POP_REGnn REG_DE ; POP DE
Z80_instr_E1: +Z80_POP_REGnn REG_HL ; POP HL
Z80_instr_F1: +Z80_POP_REGnn REG_AF ; POP AF
Z80_instr_DD_E1: +Z80_POP_REGnn REG_IX ; POP IX
Z80_instr_FD_E1: +Z80_POP_REGnn REG_IY ; POP IY
src/zvm_m65/zvm_core.s
+36 -46
View File
@@ -31,6 +31,21 @@ ZVM_store_next:
sta [PTR_DATA],z
; FALLTROUGH
!macro ZVM_DISPATCH .TAB_LO, .TAB_HI {
; Fetch and execute next opcode
jsr (VEC_fetch_value)
asl
tax
bcs @1
jmp (.TAB_LO) ; execute opcode $00-$7F
@1: jmp (.TAB_HI) ; execute opcode $80-$FF
}
; unimplemented/illegal instructions
Z80_illegal__DD:
Z80_illegal__ED:
@@ -38,64 +53,39 @@ Z80_illegal__FD:
Z80_illegal__DDCB:
Z80_illegal__FDCB:
; LD instructions with no effect
Z80_instr_40: ; LD B,B
Z80_instr_49: ; LD C,C
Z80_instr_52: ; LD D,D
Z80_instr_5B: ; LD E,E
Z80_instr_64: ; LH H,H
Z80_instr_6D: ; LD L,L
Z80_instr_7F: ; LD A,A
Z80_instr_40: ; LD B,B
Z80_instr_49: ; LD C,C
Z80_instr_52: ; LD D,D
Z80_instr_5B: ; LD E,E
Z80_instr_64: ; LD H,H
Z80_instr_6D: ; LD L,L
Z80_instr_7F: ; LD A,A
; For interrupts (not emulated as of yet)
Z80_instr_ED_46: ; IM 0
Z80_instr_ED_56: ; IM 1
Z80_instr_ED_5E: ; IM 2
Z80_instr_ED_46: ; IM 0
Z80_instr_ED_56: ; IM 1
Z80_instr_ED_5E: ; IM 2
; Real NOP
Z80_instr_00: ; NOP
Z80_instr_00: ; NOP
; Dispatch via jumptable
ZVM_next: +ZVM_DISPATCH Z80_vectab_0, Z80_vectab_1
Z80_instr_CB: +ZVM_DISPATCH Z80_vectab_CB_0, Z80_vectab_CB_1 ; #CB
Z80_instr_DD: +ZVM_DISPATCH Z80_vectab_DD_0, Z80_vectab_DD_1 ; #DD
Z80_instr_ED: +ZVM_DISPATCH Z80_vectab_ED_0, Z80_vectab_ED_1 ; #ED
Z80_instr_FD: +ZVM_DISPATCH Z80_vectab_FD_0, Z80_vectab_FD_1 ; #FD
ZVM_next: ; fetch and execute next opcode
jsr (VEC_fetch_value)
asl
tax
bcs @1
jmp (Z80_vectab_0) ; execute opcode $00-$7F
@1: jmp (Z80_vectab_1) ; execute opcode $80-$FF
Z80_instr_CB: ; #CB
jsr (VEC_fetch_value)
asl
tax
bcs @1
jmp (Z80_vectab_CB_0) ; execute opcode $00-$7F
@1: jmp (Z80_vectab_CB_1) ; execute opcode $80-$FF
Z80_instr_DD: ; #DD
jsr (VEC_fetch_value)
asl
tax
bcs @1
jmp (Z80_vectab_DD_0) ; execute opcode $00-$7F
@1: jmp (Z80_vectab_DD_1) ; execute opcode $80-$FF
Z80_instr_ED: ; #ED
jsr (VEC_fetch_value)
asl
tax
bcs @1
jmp (Z80_vectab_ED_0) ; execute opcode $00-$7F
@1: jmp (Z80_vectab_ED_1) ; execute opcode $80-$FF
Z80_instr_FD: ; #FD
jsr (VEC_fetch_value)
asl
tax
bcs @1
jmp (Z80_vectab_FD_0) ; execute opcode $00-$7F
@1: jmp (Z80_vectab_FD_1) ; execute opcode $80-$FF