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more boring opcodes work

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This commit is contained in:
FeralChild64 committed 2020-12-16 17:49:31 +01:00
1 parent 312f9a0072
commit ac3992c2a8
6 files changed
+430 -155
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src/zvm_m65/,aliases_zvm.s
+40
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@@ -0,0 +1,40 @@
!addr REG_A = $02 ; 8-bit accumulator
!addr REG_F = $03 ; 8-bit flag register
!addr REG_B = $04 ; general purpose 8-bit registers
!addr REG_C = $05
!addr REG_D = $06
!addr REG_E = $07
!addr REG_H = $08
!addr REG_L = $09
!addr REG_A_SH = $0A ; shadow registers
!addr REG_F_SH = $0B
!addr REG_B_SH = $0C
!addr REG_C_SH = $0D
!addr REG_D_SH = $0E
!addr REG_E_SH = $0F
!addr REG_H_SH = $10
!addr REG_L_SH = $11
!addr REG_IX = $12 ; 16-bit index register
!addr REG_IY = $14 ; 16-bit index register
!addr REG_SP = $16 ; 16-bit stack pointer
!addr REG_PC = $18 ; 16-bit program counter
!addr REG_I = $1A ; 8-bit interrupt vector base
!addr REG_R06 = $1B ; refresh counter, bits 0-6 (bit 7 is garbage)
!addr REG_R7 = $1C ; refresh counter, bit 7 (bits 0-6 are 0's)
!addr VEC_fetch_opcode = $60
!addr VEC_fetch_value = $62
!addr VEC_fetch_stack = $64
!addr VEC_store_stack = $66
!addr VEC_fetch_via_HL = $68
!addr VEC_store_via_HL = $6A
!addr VEC_fetch_via_IX_d = $6C
!addr VEC_fetch_via_IY_d = $6E
!addr VEC_store_via_IX_d = $70
!addr VEC_store_via_IY_d = $72
!addr VEC_fetch_via_nn = $74
!addr VEC_store_via_nn = $76
src/zvm_m65/ZVM_banking.s
+169
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@@ -0,0 +1,169 @@
;
; Z80 Virtual Machine banking support
;
ZVM_set_bank_0:
; XXX consider switchink banks using DMA list
lda #<ZVM_fetch_opcode_bank_0
sta VEC_fetch_opcode+0
lda #>ZVM_fetch_opcode_bank_0
sta VEC_fetch_opcode+1
lda #<ZVM_fetch_value_bank_0
sta VEC_fetch_value+0
lda #>ZVM_fetch_value_bank_0
sta VEC_fetch_value+1
lda #<ZVM_fetch_stack_bank_0
sta VEC_fetch_stack+0
lda #>ZVM_fetch_stack_bank_0
sta VEC_fetch_stack+1
lda #<ZVM_store_stack_bank_0
sta VEC_store_stack+0
lda #>ZVM_store_stack_bank_0
sta VEC_store_stack+1
lda #<ZVM_fetch_via_HL_bank_0
sta VEC_fetch_via_HL+0
lda #>ZVM_fetch_via_HL_bank_0
sta VEC_fetch_via_HL+1
lda #<ZVM_store_via_HL_bank_0
sta VEC_store_via_HL+0
lda #>ZVM_store_via_HL_bank_0
sta VEC_store_via_HL+1
lda #<ZVM_fetch_via_IX_d_bank_0
sta VEC_fetch_via_IX_d+0
lda #>ZVM_fetch_via_IX_d_bank_0
sta VEC_fetch_via_IX_d+1
lda #<ZVM_fetch_via_IY_d_bank_0
sta VEC_fetch_via_IY_d+0
lda #>ZVM_fetch_via_IY_d_bank_0
sta VEC_fetch_via_IY_d+1
lda #<ZVM_store_via_IX_d_bank_0
sta VEC_store_via_IX_d+0
lda #>ZVM_store_via_IX_d_bank_0
sta VEC_store_via_IX_d+1
lda #<ZVM_store_via_IY_d_bank_0
sta VEC_store_via_IY_d+0
lda #>ZVM_store_via_IY_d_bank_0
sta VEC_store_via_IY_d+1
lda #<ZVM_fetch_via_nn_bank_0
sta VEC_fetch_via_nn+0
lda #>ZVM_fetch_via_nn_bank_0
sta VEC_fetch_via_nn+1
lda #<ZVM_store_via_nn_bank_0
sta VEC_store_via_nn+0
lda #>ZVM_store_via_nn_bank_0
sta VEC_store_via_nn+1
rts
ZVM_set_bank_1:
lda #<ZVM_fetch_opcode_bank_1
sta VEC_fetch_opcode+0
lda #>ZVM_fetch_opcode_bank_1
sta VEC_fetch_opcode+1
lda #<ZVM_fetch_value_bank_1
sta VEC_fetch_value+0
lda #>ZVM_fetch_value_bank_1
sta VEC_fetch_value+1
lda #<ZVM_fetch_stack_bank_1
sta VEC_fetch_stack+0
lda #>ZVM_fetch_stack_bank_1
sta VEC_fetch_stack+1
lda #<ZVM_store_stack_bank_1
sta VEC_store_stack+0
lda #>ZVM_store_stack_bank_1
sta VEC_store_stack+1
lda #<ZVM_fetch_via_HL_bank_1
sta VEC_fetch_via_HL+0
lda #>ZVM_fetch_via_HL_bank_1
sta VEC_fetch_via_HL+1
lda #<ZVM_store_via_HL_bank_1
sta VEC_store_via_HL+0
lda #>ZVM_store_via_HL_bank_1
sta VEC_store_via_HL+1
lda #<ZVM_fetch_via_IX_d_bank_1
sta VEC_fetch_via_IX_d+0
lda #>ZVM_fetch_via_IX_d_bank_1
sta VEC_fetch_via_IX_d+1
lda #<ZVM_fetch_via_IY_d_bank_1
sta VEC_fetch_via_IY_d+0
lda #>ZVM_fetch_via_IY_d_bank_1
sta VEC_fetch_via_IY_d+1
lda #<ZVM_store_via_IX_d_bank_1
sta VEC_store_via_IX_d+0
lda #>ZVM_store_via_IX_d_bank_1
sta VEC_store_via_IX_d+1
lda #<ZVM_store_via_IY_d_bank_1
sta VEC_store_via_IY_d+0
lda #>ZVM_store_via_IY_d_bank_1
sta VEC_store_via_IY_d+1
lda #<ZVM_fetch_via_nn_bank_1
sta VEC_fetch_via_nn+0
lda #>ZVM_fetch_via_nn_bank_1
sta VEC_fetch_via_nn+1
lda #<ZVM_store_via_nn_bank_1
sta VEC_store_via_nn+0
lda #>ZVM_store_via_nn_bank_1
sta VEC_store_via_nn+1
rts
ZVM_fetch_opcode_bank_0:
; XXX implement, should return byte in .A
ZVM_fetch_opcode_bank_1:
; XXX implement, should return byte in .A
ZVM_fetch_value_bank_0:
ZVM_fetch_value_bank_1:
ZVM_fetch_stack_bank_0:
ZVM_fetch_stack_bank_1:
ZVM_store_stack_bank_0:
ZVM_store_stack_bank_1:
ZVM_fetch_via_HL_bank_0:
ZVM_fetch_via_HL_bank_1:
ZVM_store_via_HL_bank_0:
ZVM_store_via_HL_bank_1:
ZVM_fetch_via_IX_d_bank_0:
ZVM_fetch_via_IX_d_bank_1:
ZVM_fetch_via_IY_d_bank_0:
ZVM_fetch_via_IY_d_bank_1:
ZVM_store_via_IX_d_bank_0:
ZVM_store_via_IX_d_bank_1:
ZVM_store_via_IY_d_bank_0:
ZVM_store_via_IY_d_bank_1:
ZVM_fetch_via_nn_bank_0:
ZVM_fetch_via_nn_bank_1:
ZVM_store_via_nn_bank_0:
ZVM_store_via_nn_bank_1:
ZVM_store_back:
; XXX implement these
src/zvm_m65/z80_exchange.s
+63
View File
@@ -2,3 +2,66 @@
;
; Z80 data exchange instructions
;
Z80_instr_EB: ; EX DE,HL
ldx REG_D
ldy REG_H
sty REG_D
stx REG_H
ldx REG_E
ldy REG_L
sty REG_E
stx REG_L
rts
Z80_instr_08: ; EX AF,AF''
ldx REG_A
ldy REG_A_SH
sty REG_A
stx REG_A_SH
ldx REG_F
ldy REG_F_SH
sty REG_F
stx REG_F_SH
rts
Z80_instr_D9: ; EXX
ldx REG_B
ldy REG_B_SH
sty REG_B
stx REG_B_SH
ldx REG_C
ldy REG_C_SH
sty REG_C
stx REG_C_SH
ldx REG_D
ldy REG_D_SH
sty REG_D
stx REG_D_SH
ldx REG_E
ldy REG_E_SH
sty REG_E
stx REG_E_SH
ldx REG_H
ldy REG_H_SH
sty REG_H
stx REG_H_SH
ldx REG_L
ldy REG_L_SH
sty REG_L
stx REG_L_SH
rts
src/zvm_m65/z80_general.s
+5
View File
@@ -9,6 +9,11 @@ Z80_illegal__ED:
Z80_illegal__FD:
Z80_illegal__DDCB:
Z80_illegal__FDCB:
inc REG_R06 ; XXX check if this is correct
; FALLTROUGH
Z80_instr_40: ; LD B,B
Z80_instr_49: ; LD C,C
Z80_instr_52: ; LD D,D
src/zvm_m65/z80_load_8bit.s
+151 -72
View File
@@ -4,6 +4,10 @@
;
;
; load register with other register
;
Z80_instr_41: ; LD B,C
lda REG_C
@@ -34,12 +38,6 @@ Z80_instr_45: ; LD B,L
sta REG_B
rts
Z80_instr_46: ; LD B,(HL)
jsr (VEC_fetch_via_HL)
sta REG_B
rts
Z80_instr_47: ; LD B,A
lda REG_A
@@ -76,15 +74,9 @@ Z80_instr_4D: ; LD C,L
sta REG_C
rts
Z80_instr_4E: ; LD C,(HL)
jsr (VEC_fetch_via_HL)
sta REG_C
rts
Z80_instr_4F: ; LD C,A
lda REG_Z
lda REG_A
sta REG_C
rts
@@ -118,12 +110,6 @@ Z80_instr_55: ; LD D,L
sta REG_D
rts
Z80_instr_56: ; LD D,(HL)
jsr (VEC_fetch_via_HL)
sta REG_D
rts
Z80_instr_57: ; LD D,A
lda REG_A
@@ -160,12 +146,6 @@ Z80_instr_5D: ; LD E,L
sta REG_E
rts
Z80_instr_5E: ; LD E,(HL)
jsr (VEC_fetch_via_HL)
sta REG_E
rts
Z80_instr_5F: ; LD E,A
lda REG_A
@@ -202,12 +182,6 @@ Z80_instr_65: ; LD H,L
sta REG_H
rts
Z80_instr_66: ; LD H,(HL)
jsr (VEC_fetch_via_HL)
sta REG_H
rts
Z80_instr_67: ; LD H,A
lda REG_A
@@ -244,53 +218,12 @@ Z80_instr_6C: ; LD L,H
sta REG_L
rts
Z80_instr_6E: ; LD L,(HL)
jsr (VEC_fetch_via_HL)
sta REG_L
rts
Z80_instr_6F: ; LD L,A
lda REG_A
sta REG_L
rts
Z80_instr_70: ; LD (HL),B
lda REG_B
jmp (VEC_store_via_HL)
Z80_instr_71: ; LD (HL),C
lda REG_C
jmp (VEC_store_via_HL)
Z80_instr_72: ; LD (HL),D
lda REG_D
jmp (VEC_store_via_HL)
Z80_instr_73: ; LD (HL),E
lda REG_E
jmp (VEC_store_via_HL)
Z80_instr_74: ; LD (HL),H
lda REG_H
jmp (VEC_store_via_HL)
Z80_instr_75: ; LD (HL),L
lda REG_L
jmp (VEC_store_via_HL)
Z80_instr_77: ; LD (HL),A
lda REG_A
jmp (VEC_store_via_HL)
Z80_instr_78: ; LD A,B
lda REG_B
@@ -327,8 +260,154 @@ Z80_instr_7D: ; LD A,L
sta REG_A
rts
;
; load register with immediate value
;
Z80_instr_06: ; LD B,n
jsr VEC_fetch_value
sta REG_B
rts
Z80_instr_0E: ; LD C,n
jsr VEC_fetch_value
sta REG_C
rts
Z80_instr_16: ; LD D,n
jsr VEC_fetch_value
sta REG_D
rts
Z80_instr_1E: ; LD E,n
jsr VEC_fetch_value
sta REG_E
rts
Z80_instr_26: ; LD H,n
jsr VEC_fetch_value
sta REG_H
rts
Z80_instr_2E: ; LD L,n
jsr VEC_fetch_value
sta REG_L
rts
Z80_instr_3E: ; LD A,n
jsr VEC_fetch_value
sta REG_A
rts
;
; load register with memory content (via HL)
;
Z80_instr_46: ; LD B,(HL)
jsr (VEC_fetch_via_HL)
sta REG_B
rts
Z80_instr_4E: ; LD C,(HL)
jsr (VEC_fetch_via_HL)
sta REG_C
rts
Z80_instr_56: ; LD D,(HL)
jsr (VEC_fetch_via_HL)
sta REG_D
rts
Z80_instr_5E: ; LD E,(HL)
jsr (VEC_fetch_via_HL)
sta REG_E
rts
Z80_instr_66: ; LD H,(HL)
jsr (VEC_fetch_via_HL)
sta REG_H
rts
Z80_instr_6E: ; LD L,(HL)
jsr (VEC_fetch_via_HL)
sta REG_L
rts
Z80_instr_7E: ; LD A,(HL)
jsr (VEC_fetch_via_HL)
sta REG_A
rts
; XXX put here LD r,(IX+d) family
; XXX put here LD r,(IY+d) family
;
; load memory content (via HL) with register
;
Z80_instr_70: ; LD (HL),B
lda REG_B
jmp (VEC_store_via_HL)
Z80_instr_71: ; LD (HL),C
lda REG_C
jmp (VEC_store_via_HL)
Z80_instr_72: ; LD (HL),D
lda REG_D
jmp (VEC_store_via_HL)
Z80_instr_73: ; LD (HL),E
lda REG_E
jmp (VEC_store_via_HL)
Z80_instr_74: ; LD (HL),H
lda REG_H
jmp (VEC_store_via_HL)
Z80_instr_75: ; LD (HL),L
lda REG_L
jmp (VEC_store_via_HL)
Z80_instr_77: ; LD (HL),A
lda REG_A
jmp (VEC_store_via_HL)
; XXX put here LD (IX+d),r family
; XXX put here LD (IY+d),r family
;
; load memory content (via HL) with immediate value
;
Z80_instr_36: ; LD (HL),n
jsr VEC_fetch_value
jmp (VEC_store_via_HL)
; XXX put here LD (IX+d),n family
; XXX put here LD (IY+d),n family
; XXX put here LD A,(BC) / LD A,(DE) / LD A,(nn) / LD (BC), A / LD (DE),A / LD (nn),A
; XXX put here LD A,I / LD A,R
; XXX put here LD I,A / LD R,A
src/zvm_m65/zvm_core.s
+2 -83
View File
@@ -3,38 +3,6 @@
; Z80 Virtual Machine core routines
;
!addr REG_A = $02 ; 8-bit accumulator
!addr REG_F = $03 ; 8-bit flag register
!addr REG_B = $04 ; general purpose 8-bit registers
!addr REG_C = $05
!addr REG_D = $06
!addr REG_E = $07
!addr REG_H = $08
!addr REG_L = $09
!addr REG_A_SH = $0A ; shadow registers
!addr REG_F_SH = $0B
!addr REG_B_SH = $0C
!addr REG_C_SH = $0D
!addr REG_D_SH = $0E
!addr REG_E_SH = $0F
!addr REG_H_SH = $10
!addr REG_L_SH = $11
!addr REG_IX = $12 ; 16-bit index register
!addr REG_IY = $14 ; 16-bit index register
!addr REG_SP = $16 ; 16-bit stack pointer
!addr REG_PC = $18 ; 16-bit program counter
!addr REG_I = $1A ; 8-bit interrupt vector base
!addr REG_R06 = $1B ; refresh counter, bits 0-6 (bit 7 is garbage)
!addr REG_R7 = $1C ; refresh counter, bit 7 (bits 0-6 are 0's)
!addr VEC_fetch_opcode = $1D
!addr VEC_fetch_via_HL = $1F
!addr VEC_store_via_HL = $21
ZVM_entry:
jsr ZVM_init
@@ -56,39 +24,13 @@ ZVM_init:
; XXX what is the initial SP value?
; XXX clean memory
; FALLTROUGH
jmp ZVM_set_bank_0
ZVM_bank_0:
lda #<ZVM_fetch_instr_bank_0
sta VEC_fetch_opcode+0
lda #>ZVM_fetch_instr_bank_0
sta VEC_fetch_opcode+1
rts
ZVM_bank_1:
lda #<ZVM_fetch_instr_bank_1
sta VEC_fetch_opcode+0
lda #>ZVM_fetch_instr_bank_1
sta VEC_fetch_opcode+1
rts
ZVM_fetch_opcode_bank_0:
; XXX implement, should return byte in .A
ZVM_fetch_opcode_bank_1:
; XXX implement, should return byte in .A
ZVM_run:
; CPU main loop
jsr (VEC_fetch_instr)
jsr (VEC_fetch_opcode)
asl
bcs @1
@@ -102,18 +44,6 @@ ZVM_run:
;
; Not implemented yet - XXX implement them!
;
@@ -123,15 +53,12 @@ Z80_instr_02: ; LD (BC),A
Z80_instr_03: ; INC BC
Z80_instr_04: ; INC B
Z80_instr_05: ; DEC B
Z80_instr_06: ; LD B,n
Z80_instr_07: ; RLCA
Z80_instr_08: ; EX AF,AF''
Z80_instr_09: ; ADD HL,BC
Z80_instr_0A: ; LD A,(BC)
Z80_instr_0B: ; DEC BC
Z80_instr_0C: ; INC C
Z80_instr_0D: ; DEC C
Z80_instr_0E: ; LD C,n
Z80_instr_0F: ; RRCA
Z80_instr_10: ; DJNZ e
Z80_instr_11: ; LD DE,nn
@@ -139,7 +66,6 @@ Z80_instr_12: ; LD (DE),A
Z80_instr_13: ; INC DE
Z80_instr_14: ; INC D
Z80_instr_15: ; DEC D
Z80_instr_16: ; LD D,n
Z80_instr_17: ; RLA
Z80_instr_18: ; JR e
Z80_instr_19: ; ADD HL,DE
@@ -147,7 +73,6 @@ Z80_instr_1A: ; LD A,(DE)
Z80_instr_1B: ; DEC DE
Z80_instr_1C: ; INC E
Z80_instr_1D: ; DEC E
Z80_instr_1E: ; LD E,n
Z80_instr_1F: ; RRA
Z80_instr_20: ; JR NZ,e
Z80_instr_21: ; LD HL,nn
@@ -155,7 +80,6 @@ Z80_instr_22: ; LD (nn),HL
Z80_instr_23: ; INC HL
Z80_instr_24: ; INC H
Z80_instr_25: ; DEC H
Z80_instr_26: ; LD H,n
Z80_instr_27: ; DAA
Z80_instr_28: ; JR Z,e
Z80_instr_29: ; ADD HL,HL
@@ -163,7 +87,6 @@ Z80_instr_2A: ; LD HL,(nn)
Z80_instr_2B: ; DEC HL
Z80_instr_2C: ; INC L
Z80_instr_2D: ; DEC L
Z80_instr_2E: ; LD L,n
Z80_instr_2F: ; CPL
Z80_instr_30: ; JR NC,e
Z80_instr_31: ; LD SP,nn
@@ -171,7 +94,6 @@ Z80_instr_32: ; LD (nn),A
Z80_instr_33: ; INC SP
Z80_instr_34: ; INC (HL)
Z80_instr_35: ; DEC (HL)
Z80_instr_36: ; LD (HL),n
Z80_instr_37: ; SCF
Z80_instr_38: ; JR C,e
Z80_instr_39: ; ADD HL,SP
@@ -179,7 +101,6 @@ Z80_instr_3A: ; LD A,(nn)
Z80_instr_3B: ; DEC SP
Z80_instr_3C: ; INC A
Z80_instr_3D: ; DEC A
Z80_instr_3E: ; LD A,n
Z80_instr_3F: ; CCF
Z80_instr_76: ; HALT
Z80_instr_80: ; ADD A,B
@@ -271,7 +192,6 @@ Z80_instr_D5: ; PUSH DE
Z80_instr_D6: ; SUB n
Z80_instr_D7: ; RST 10H
Z80_instr_D8: ; RET C
Z80_instr_D9: ; EXX
Z80_instr_DA: ; JP C,nn
Z80_instr_DB: ; IN A,(n)
Z80_instr_DC: ; CALL C,nn
@@ -289,7 +209,6 @@ Z80_instr_E7: ; RST 20H
Z80_instr_E8: ; RET PE
Z80_instr_E9: ; JP (HL)
Z80_instr_EA: ; JP PE,nn
Z80_instr_EB: ; EX DE,HL
Z80_instr_EC: ; CALL PE,nn
Z80_instr_ED: ; #ED
Z80_instr_EE: ; XOR n