added remaining Z80 illegal opcodes

2020-12-22 19:51:23 +01:00
1 parent b79f01582d
commit cfd875de0b
@@ -369,7 +369,314 @@ Z80_illeg_xDCB_C5: ; SET 0,(IXY+d),L
 Z80_illeg_xDCB_C7: ; SET 0,(IXY+d),A


-
 	jmp ZVM_next ; XXX

 	; XXX add illegal instructions for combination of prefixes
+
+	; XXX include these in the table, add mnemonics
+
+Z80_illeg_ED_63:
+Z80_illeg_ED_6B:
+Z80_illeg_DD_24:
+Z80_illeg_DD_25:
+Z80_illeg_DD_26:
+Z80_illeg_DD_2C:
+Z80_illeg_DD_2D:
+Z80_illeg_DD_2E:
+Z80_illeg_DD_44:
+Z80_illeg_DD_45:
+Z80_illeg_DD_4C:
+Z80_illeg_DD_4D:
+Z80_illeg_DD_54:
+Z80_illeg_DD_55:
+Z80_illeg_DD_5C:
+Z80_illeg_DD_5D:
+Z80_illeg_DD_60:
+Z80_illeg_DD_61:
+Z80_illeg_DD_62:
+Z80_illeg_DD_63:
+Z80_illeg_DD_64:
+Z80_illeg_DD_65:
+Z80_illeg_DD_67:
+Z80_illeg_DD_68:
+Z80_illeg_DD_69:
+Z80_illeg_DD_6A:
+Z80_illeg_DD_6B:
+Z80_illeg_DD_6C:
+Z80_illeg_DD_6D:
+Z80_illeg_DD_6F:
+Z80_illeg_DD_7C:
+Z80_illeg_DD_6D:
+Z80_illeg_DD_84:
+Z80_illeg_DD_85:
+Z80_illeg_DD_8C:
+Z80_illeg_DD_8D:
+Z80_illeg_DD_94:
+Z80_illeg_DD_95:
+Z80_illeg_DD_9C:
+Z80_illeg_DD_9D:
+Z80_illeg_DD_A4:
+Z80_illeg_DD_A5:
+Z80_illeg_DD_AC:
+Z80_illeg_DD_AD:
+Z80_illeg_DD_B4:
+Z80_illeg_DD_B5:
+Z80_illeg_DD_BC:
+Z80_illeg_DD_BD:
+Z80_illeg_FD_24:
+Z80_illeg_FD_25:
+Z80_illeg_FD_26:
+Z80_illeg_FD_2C:
+Z80_illeg_FD_2D:
+Z80_illeg_FD_2E:
+Z80_illeg_FD_44:
+Z80_illeg_FD_45:
+Z80_illeg_FD_4C:
+Z80_illeg_FD_4D:
+Z80_illeg_FD_54:
+Z80_illeg_FD_55:
+Z80_illeg_FD_5C:
+Z80_illeg_FD_5D:
+Z80_illeg_FD_60:
+Z80_illeg_FD_61:
+Z80_illeg_FD_62:
+Z80_illeg_FD_63:
+Z80_illeg_FD_64:
+Z80_illeg_FD_65:
+Z80_illeg_FD_67:
+Z80_illeg_FD_68:
+Z80_illeg_FD_69:
+Z80_illeg_FD_6A:
+Z80_illeg_FD_6B:
+Z80_illeg_FD_6C:
+Z80_illeg_FD_6D:
+Z80_illeg_FD_6F:
+Z80_illeg_FD_7C:
+Z80_illeg_FD_6D:
+Z80_illeg_FD_84:
+Z80_illeg_FD_85:
+Z80_illeg_FD_8C:
+Z80_illeg_FD_8D:
+Z80_illeg_FD_94:
+Z80_illeg_FD_95:
+Z80_illeg_FD_9C:
+Z80_illeg_FD_9D:
+Z80_illeg_FD_A4:
+Z80_illeg_FD_A5:
+Z80_illeg_FD_AC:
+Z80_illeg_FD_AD:
+Z80_illeg_FD_B4:
+Z80_illeg_FD_B5:
+Z80_illeg_FD_BC:
+Z80_illeg_FD_BD:
+Z80_illeg_xDCB_00:
+Z80_illeg_xDCB_01:
+Z80_illeg_xDCB_02:
+Z80_illeg_xDCB_03:
+Z80_illeg_xDCB_04:
+Z80_illeg_xDCB_05:
+Z80_illeg_xDCB_07:
+Z80_illeg_xDCB_08:
+Z80_illeg_xDCB_09:
+Z80_illeg_xDCB_0A:
+Z80_illeg_xDCB_0B:
+Z80_illeg_xDCB_0C:
+Z80_illeg_xDCB_0D:
+Z80_illeg_xDCB_0F:
+Z80_illeg_xDCB_10:
+Z80_illeg_xDCB_11:
+Z80_illeg_xDCB_12:
+Z80_illeg_xDCB_13:
+Z80_illeg_xDCB_14:
+Z80_illeg_xDCB_15:
+Z80_illeg_xDCB_17:
+Z80_illeg_xDCB_18:
+Z80_illeg_xDCB_19:
+Z80_illeg_xDCB_1A:
+Z80_illeg_xDCB_1B:
+Z80_illeg_xDCB_1C:
+Z80_illeg_xDCB_1D:
+Z80_illeg_xDCB_1F:
+Z80_illeg_xDCB_20:
+Z80_illeg_xDCB_21:
+Z80_illeg_xDCB_22:
+Z80_illeg_xDCB_23:
+Z80_illeg_xDCB_24:
+Z80_illeg_xDCB_25:
+Z80_illeg_xDCB_27:
+Z80_illeg_xDCB_28:
+Z80_illeg_xDCB_29:
+Z80_illeg_xDCB_2A:
+Z80_illeg_xDCB_2B:
+Z80_illeg_xDCB_2C:
+Z80_illeg_xDCB_2D:
+Z80_illeg_xDCB_2F:
+Z80_illeg_xDCB_30:
+Z80_illeg_xDCB_31:
+Z80_illeg_xDCB_32:
+Z80_illeg_xDCB_33:
+Z80_illeg_xDCB_34:
+Z80_illeg_xDCB_35:
+Z80_illeg_xDCB_36:
+Z80_illeg_xDCB_37:
+Z80_illeg_xDCB_38:
+Z80_illeg_xDCB_39:
+Z80_illeg_xDCB_3A:
+Z80_illeg_xDCB_3B:
+Z80_illeg_xDCB_3C:
+Z80_illeg_xDCB_3D:
+Z80_illeg_xDCB_3F:
+Z80_illeg_xDCB_40:
+Z80_illeg_xDCB_41:
+Z80_illeg_xDCB_42:
+Z80_illeg_xDCB_43:
+Z80_illeg_xDCB_44:
+Z80_illeg_xDCB_45:
+Z80_illeg_xDCB_47:
+Z80_illeg_xDCB_48:
+Z80_illeg_xDCB_49:
+Z80_illeg_xDCB_4A:
+Z80_illeg_xDCB_4B:
+Z80_illeg_xDCB_4C:
+Z80_illeg_xDCB_4D:
+Z80_illeg_xDCB_4F:
+Z80_illeg_xDCB_50:
+Z80_illeg_xDCB_51:
+Z80_illeg_xDCB_52:
+Z80_illeg_xDCB_53:
+Z80_illeg_xDCB_54:
+Z80_illeg_xDCB_55:
+Z80_illeg_xDCB_57:
+Z80_illeg_xDCB_58:
+Z80_illeg_xDCB_59:
+Z80_illeg_xDCB_5A:
+Z80_illeg_xDCB_5B:
+Z80_illeg_xDCB_5C:
+Z80_illeg_xDCB_5D:
+Z80_illeg_xDCB_5F:
+Z80_illeg_xDCB_60:
+Z80_illeg_xDCB_61:
+Z80_illeg_xDCB_62:
+Z80_illeg_xDCB_63:
+Z80_illeg_xDCB_64:
+Z80_illeg_xDCB_65:
+Z80_illeg_xDCB_67:
+Z80_illeg_xDCB_68:
+Z80_illeg_xDCB_69:
+Z80_illeg_xDCB_6A:
+Z80_illeg_xDCB_6B:
+Z80_illeg_xDCB_6C:
+Z80_illeg_xDCB_6D:
+Z80_illeg_xDCB_6F:
+Z80_illeg_xDCB_70:
+Z80_illeg_xDCB_71:
+Z80_illeg_xDCB_72:
+Z80_illeg_xDCB_73:
+Z80_illeg_xDCB_74:
+Z80_illeg_xDCB_75:
+Z80_illeg_xDCB_77:
+Z80_illeg_xDCB_80:
+Z80_illeg_xDCB_81:
+Z80_illeg_xDCB_82:
+Z80_illeg_xDCB_83:
+Z80_illeg_xDCB_84:
+Z80_illeg_xDCB_85:
+Z80_illeg_xDCB_87:
+Z80_illeg_xDCB_88:
+Z80_illeg_xDCB_89:
+Z80_illeg_xDCB_8A:
+Z80_illeg_xDCB_8B:
+Z80_illeg_xDCB_8C:
+Z80_illeg_xDCB_8D:
+Z80_illeg_xDCB_8F:
+Z80_illeg_xDCB_90:
+Z80_illeg_xDCB_91:
+Z80_illeg_xDCB_92:
+Z80_illeg_xDCB_93:
+Z80_illeg_xDCB_94:
+Z80_illeg_xDCB_95:
+Z80_illeg_xDCB_97:
+Z80_illeg_xDCB_98:
+Z80_illeg_xDCB_99:
+Z80_illeg_xDCB_9A:
+Z80_illeg_xDCB_9B:
+Z80_illeg_xDCB_9C:
+Z80_illeg_xDCB_9D:
+Z80_illeg_xDCB_9F:
+Z80_illeg_xDCB_A0:
+Z80_illeg_xDCB_A1:
+Z80_illeg_xDCB_A2:
+Z80_illeg_xDCB_A3:
+Z80_illeg_xDCB_A4:
+Z80_illeg_xDCB_A5:
+Z80_illeg_xDCB_A7:
+Z80_illeg_xDCB_A8:
+Z80_illeg_xDCB_A9:
+Z80_illeg_xDCB_AA:
+Z80_illeg_xDCB_AB:
+Z80_illeg_xDCB_AC:
+Z80_illeg_xDCB_AD:
+Z80_illeg_xDCB_AF:
+Z80_illeg_xDCB_B0:
+Z80_illeg_xDCB_B1:
+Z80_illeg_xDCB_B2:
+Z80_illeg_xDCB_B3:
+Z80_illeg_xDCB_B4:
+Z80_illeg_xDCB_B5:
+Z80_illeg_xDCB_B7:
+Z80_illeg_xDCB_B8:
+Z80_illeg_xDCB_B9:
+Z80_illeg_xDCB_BA:
+Z80_illeg_xDCB_BB:
+Z80_illeg_xDCB_BC:
+Z80_illeg_xDCB_BD:
+Z80_illeg_xDCB_BF:
+Z80_illeg_xDCB_C8:
+Z80_illeg_xDCB_C9:
+Z80_illeg_xDCB_CA:
+Z80_illeg_xDCB_CB:
+Z80_illeg_xDCB_CC:
+Z80_illeg_xDCB_CD:
+Z80_illeg_xDCB_CF:
+Z80_illeg_xDCB_D0:
+Z80_illeg_xDCB_D1:
+Z80_illeg_xDCB_D2:
+Z80_illeg_xDCB_D3:
+Z80_illeg_xDCB_D4:
+Z80_illeg_xDCB_D5:
+Z80_illeg_xDCB_D7:
+Z80_illeg_xDCB_D8:
+Z80_illeg_xDCB_D9:
+Z80_illeg_xDCB_DA:
+Z80_illeg_xDCB_DB:
+Z80_illeg_xDCB_DC:
+Z80_illeg_xDCB_DD:
+Z80_illeg_xDCB_DF:
+Z80_illeg_xDCB_E0:
+Z80_illeg_xDCB_E1:
+Z80_illeg_xDCB_E2:
+Z80_illeg_xDCB_E3:
+Z80_illeg_xDCB_E4:
+Z80_illeg_xDCB_E5:
+Z80_illeg_xDCB_E7:
+Z80_illeg_xDCB_E8:
+Z80_illeg_xDCB_E9:
+Z80_illeg_xDCB_EA:
+Z80_illeg_xDCB_EB:
+Z80_illeg_xDCB_EC:
+Z80_illeg_xDCB_ED:
+Z80_illeg_xDCB_EF:
+Z80_illeg_xDCB_F0:
+Z80_illeg_xDCB_F1:
+Z80_illeg_xDCB_F2:
+Z80_illeg_xDCB_F3:
+Z80_illeg_xDCB_F4:
+Z80_illeg_xDCB_F5:
+Z80_illeg_xDCB_F7:
+Z80_illeg_xDCB_F8:
+Z80_illeg_xDCB_F9:
+Z80_illeg_xDCB_FA:
+Z80_illeg_xDCB_FB:
+Z80_illeg_xDCB_FC:
+Z80_illeg_xDCB_FD:
+Z80_illeg_xDCB_FF: