few more Z80 instructions

src/zvm_m65/,aliases_zvm.s

@@ -27,11 +27,11 @@
 !addr REG_R7             = $1C    ; refresh counter, bit 7 (bits 0-6 are 0's)
 
 !addr PTR_IXY_d          = $1D    ; 16-bit calculated address IX+d / IY+d  XXX - important!!!
-!addr PTR_DATA           = $1D    ; data source address   XXX is it OK to use the same one?
+!addr PTR_DATA           = $1F    ; data source address                    XXX - important!!!
 
 
-!addr REG_IFF1           = $1F    ; interrupt flip-flop flag 1
-!addr REG_IFF2           = $20    ; interrupt flip-flop flag 2
+!addr REG_IFF1           = $23    ; interrupt flip-flop flag 1
+!addr REG_IFF2           = $24    ; interrupt flip-flop flag 2
 
 !addr VEC_fetch_value    = $60
 !addr VEC_fetch_stack    = $62

src/zvm_m65/z80_instr_load_8bit.s

@@ -409,5 +409,51 @@ Z80_instr_36:      ; LD (HL),n
 ; XXX put here LD (IX+d),n family
 ; XXX put here LD (IY+d),n family
 ; XXX put here LD A,(BC) / LD A,(DE) / LD A,(nn) / LD (BC), A / LD (DE),A / LD (nn),A
-; XXX put here LD A,I / LD A,R
-; XXX put here LD I,A / LD R,A
+
+Z80_instr_ED_57:   ; LD A,I
+
+	lda REG_F
+	and #($FF - Z80_SF - Z80_ZF - Z80_HF - Z80_PF - Z80_NF)
+	ora REG_IFF2
+	sta REG_F
+
+	lda REG_I
+	sta REG_A
+	bpl @1
+	+Z80_PUT_1_SF
+@1:
+	+bne ZVM_next
+	+Z80_PUT_1_ZF
+	jmp ZVM_next
+
+Z80_instr_ED_5F:   ; LD A,R
+
+	lda REG_F
+	and #($FF - Z80_SF - Z80_ZF - Z80_HF - Z80_PF - Z80_NF)
+	ora REG_IFF2
+	sta REG_F
+
+	lda REG_R06
+	and #%01111111
+	ora REG_R7
+	sta REG_A
+	bpl @1
+	+Z80_PUT_1_SF
+@1:
+	+bne ZVM_next
+	+Z80_PUT_1_ZF
+	jmp ZVM_next
+
+Z80_instr_ED_47:   ; LD I,A
+
+	lda REG_A
+	sta REG_I
+	jmp ZVM_next
+
+Z80_instr_ED_4F:   ; LD R,A
+
+	lda REG_A
+	sta REG_R06
+	and #%01111111
+	sta REG_R7
+	jmp ZVM_next

src/zvm_m65/zvm_core.s

@@ -338,23 +338,19 @@ Z80_instr_ED_42:   ; SBC HL,BC
 Z80_instr_ED_43:   ; LD (nn),BC
 Z80_instr_ED_44:   ; NEG
 Z80_instr_ED_45:   ; RETN
-Z80_instr_ED_47:   ; LD I,A
 Z80_instr_ED_48:   ; IN C,(C)
 Z80_instr_ED_49:   ; OUT (C),C
 Z80_instr_ED_4A:   ; ADC HL,BC
 Z80_instr_ED_4B:   ; LD BC,(nn)
 Z80_instr_ED_4D:   ; RETTI
-Z80_instr_ED_4F:   ; LD R,A
 Z80_instr_ED_50:   ; IN D,(C)
 Z80_instr_ED_51:   ; OUT (C),D
 Z80_instr_ED_52:   ; SBC HL,DE
 Z80_instr_ED_53:   ; LD (nn),DE
-Z80_instr_ED_57:   ; LD A,I
 Z80_instr_ED_58:   ; IN E,(C)
 Z80_instr_ED_59:   ; OUT (C),E
 Z80_instr_ED_5A:   ; ADC HL,DE
 Z80_instr_ED_5B:   ; LD DE,(nn)
-Z80_instr_ED_5F:   ; LD A,R
 Z80_instr_ED_60:   ; IN H,(C)
 Z80_instr_ED_61:   ; OUT (C),H
 Z80_instr_ED_62:   ; SBC HL,HL