several features are now optional, added legacy BASIC memory model
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@@ -10,6 +10,8 @@
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// VIC-II registers
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.label VIC_BASE = $D000 // base address of the chip
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.label VIC_SP0X = $D000
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.label VIC_SP0Y = $D001
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.label VIC_SP1X = $D002
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@@ -62,6 +64,8 @@
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// SID registers
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.label SID_BASE = $D400 // base address of the chip
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.label SID_FRELO1 = $D400
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.label SID_FREHI1 = $D401
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.label SID_PWLO1 = $D402
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@@ -97,6 +101,8 @@
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// CIA #1 registers
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.label CIA1_BASE = $DC00 // base address of the chip
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.label CIA1_PRA = $DC00
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.label CIA1_PRB = $DC01
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.label CIA1_DDRA = $DC02
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@@ -119,6 +125,8 @@
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// CIA #2 registers
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.label CIA2_BASE = $DD00 // base address of the chip
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.label CIA2_PRA = $DD00 // VIC bank switching and IEC port
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.label CIA2_PRB = $DD01
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.label CIA2_DDRA = $DD02
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