several features are now optional, added legacy BASIC memory model

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FeralChild64 committed 2019-09-11 19:21:02 +02:00
1 parent 49e8b75b85
commit ed51a62f32
30 files changed
+555 -72

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@@ -10,6 +10,8 @@
// VIC-II registers
.label VIC_BASE = $D000 // base address of the chip
.label VIC_SP0X = $D000
.label VIC_SP0Y = $D001
.label VIC_SP1X = $D002
@@ -62,6 +64,8 @@
// SID registers
.label SID_BASE = $D400 // base address of the chip
.label SID_FRELO1 = $D400
.label SID_FREHI1 = $D401
.label SID_PWLO1 = $D402
@@ -97,6 +101,8 @@
// CIA #1 registers
.label CIA1_BASE = $DC00 // base address of the chip
.label CIA1_PRA = $DC00
.label CIA1_PRB = $DC01
.label CIA1_DDRA = $DC02
@@ -119,6 +125,8 @@
// CIA #2 registers
.label CIA2_BASE = $DD00 // base address of the chip
.label CIA2_PRA = $DD00 // VIC bank switching and IEC port
.label CIA2_PRB = $DD01
.label CIA2_DDRA = $DD02