more work on IEC, some refactoring and temporary breakage
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@@ -117,3 +117,13 @@
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.alias poke_under_roms tiny_nmi_handler+poke_under_roms_routine-tiny_nmi_handler_routine
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.alias memmap_allram tiny_nmi_handler+memmap_allram_routine-tiny_nmi_handler_routine
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.alias memmap_normal tiny_nmi_handler+memmap_normal_routine-tiny_nmi_handler_routine
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;; CIA#2 - https://www.c64-wiki.com/wiki/CIA#CIA_2
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.alias CI2PRA $DD00 ; VIC bank switching and IEC port
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.alias BIT_CI2PRA_ATN_OUT $08 ; 1 - low (pulled), 0 - high (released)
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.alias BIT_CI2PRA_CLK_OUT $10 ; 1 - low (pulled), 0 - high (released)
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.alias BIT_CI2PRA_DAT_OUT $20 ; 1 - low (pulled), 0 - high (released)
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.alias BIT_CI2PRA_CLK_IN $40 ; 0 - low (pulled), 1 - high (released)
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.alias BIT_CI2PRA_DAT_IN $80 ; 0 - low (pulled), 1 - high (released)
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@@ -39,4 +39,7 @@ ioinit:
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lda #$3b
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sta $dd02
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;; Set IEC bus oto its initial idle state
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jsr iec_set_idle
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rts
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@@ -1,5 +0,0 @@
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iec_assert_atn:
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lda $dd00
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ora #$08
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sta $dd00
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rts
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@@ -1,6 +0,0 @@
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iec_assert_clk_and_data:
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lda $dd00
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and #$0b
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ora #$30
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sta $dd00
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rts
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@@ -1,6 +0,0 @@
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iec_assert_clk_release_data:
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lda $dd00
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and #$0b
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ora #$10
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sta $dd00
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rts
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@@ -1,5 +0,0 @@
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iec_assert_data:
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lda $dd00
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ora #$20
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sta $dd00
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rts
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@@ -0,0 +1,7 @@
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iec_pull_atn_clk_release_data:
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lda CI2PRA
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ora #BIT_CI2PRA_ATN_OUT + BIT_CI2PRA_CLK_OUT ; pull
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and #$FF - BIT_CI2PRA_DAT_OUT ; release
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sta CI2PRA
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rts
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@@ -0,0 +1,7 @@
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iec_pull_clk_release_data:
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lda CI2PRA
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ora #BIT_CI2PRA_CLK_OUT ; pull
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and #$FF - BIT_CI2PRA_DAT_OUT ; release
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sta CI2PRA
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rts
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@@ -1,11 +0,0 @@
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iec_release_atn:
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lda $dd00
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and #$f7
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sta $dd00
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;; Also clear EOI marker
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lda IOSTATUS
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and #$bf
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sta IOSTATUS
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rts
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@@ -1,5 +0,0 @@
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iec_release_clk:
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lda $dd00
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and #$2b
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sta $dd00
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rts
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@@ -1,6 +0,0 @@
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iec_release_clk_and_data:
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lda $DD00
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and #$0b
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sta $DD00
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rts
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@@ -0,0 +1,6 @@
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iec_release_clk_data:
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lda CI2PRA
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and #$FF - BIT_CI2PRA_CLK_OUT - BIT_CI2PRA_DAT_OUT ; release
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sta CI2PRA
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rts
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@@ -0,0 +1,7 @@
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iec_release_clk_pull_data:
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lda CI2PRA
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and #$FF - BIT_CI2PRA_CLK_OUT ; release
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ora #BIT_CI2PRA_DAT_OUT ; pull
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sta CI2PRA
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rts
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+95
-91
@@ -3,112 +3,116 @@
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;; page 11.
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;; XXX rework this, according to pagetable.com
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iec_rx_byte:
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;; First, we wait for the talker to release the CLK line.
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jsr iec_wait_for_clock_release
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;; We then release the data line
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;; (We can use this routine, since we weren't holding CLK, anyway)
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jsr iec_release_clk_and_data
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;; Wait for talker to assert CLK.
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;; If >200usec, then it is EOI and we have to assert the
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;; DATA line for 60 usec to tell the TALKER that we have
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;; acknowledged the EOI.
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ldx #20
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iec_rx_clk_wait:
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;; Loop takes 11 usec, so ~20 iterations for 200usec timeout
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lda $dd00
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rol
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bpl not_eoi
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dex
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cpx #$21
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bne not_rx_timeout
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;; Time out waiting for CLK to assert again.
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;; = error
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sec
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rts
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; ;; First, we wait for the talker to release the CLK line.
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; ;; XXX jsr iec_wait_for_clock_release
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; ;; We then release the data line
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; ;; (We can use this routine, since we weren't holding CLK, anyway)
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; jsr iec_release_clk_and_data
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; ;; Wait for talker to assert CLK.
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; ;; If >200usec, then it is EOI and we have to assert the
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; ;; DATA line for 60 usec to tell the TALKER that we have
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; ;; acknowledged the EOI.
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; ldx #20
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iec_rx_clk_wait:
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; ;; Loop takes 11 usec, so ~20 iterations for 200usec timeout
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; lda $dd00
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; rol
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; bpl not_eoi
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; dex
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; cpx #$21
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; bne not_rx_timeout
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; ;; Time out waiting for CLK to assert again.
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; ;; = error
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; sec
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; rts
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not_rx_timeout:
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cpx #$00
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bpl iec_rx_clk_wait
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; cpx #$00
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; bpl iec_rx_clk_wait
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;; Remember EOI condition
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lda IOSTATUS
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ora #$40
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sta IOSTATUS
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; ;; Remember EOI condition
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; lda IOSTATUS
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; ora #$40
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; sta IOSTATUS
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;; EOI timeout: So pulse DATA line for 60 usec
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jsr iec_assert_data
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jsr iec_wait60us
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jsr iec_release_clk_and_data
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; ;; EOI timeout: So pulse DATA line for 60 usec
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; jsr iec_assert_data
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; jsr iec_wait60us
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; jsr iec_release_clk_and_data
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;; And still wait for CLK to be asserted
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;; XXX - This will cause periodic EOI pulses if the sender takes too long.
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;; That is probably ok.
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ldx #$7f
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jmp iec_rx_clk_wait
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; ;; And still wait for CLK to be asserted
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; ;; XXX - This will cause periodic EOI pulses if the sender takes too long.
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; ;; That is probably ok.
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; ldx #$7f
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; jmp iec_rx_clk_wait
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not_eoi:
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;; CLK is now low. Latch input bits in on rising edge
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;; of CLK, eight times for eight bits.
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ldx #7
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; ;; CLK is now low. Latch input bits in on rising edge
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; ;; of CLK, eight times for eight bits.
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; ldx #7
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; ;; Get empty byte to load into.
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; lda #$00
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; pha
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;; Get empty byte to load into.
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lda #$00
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pha
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iec_rx_bit_loop:
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;; Wait for CLK to release
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;; jsr iec_wait_for_clock_release
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;; (we do this implicitly below, with a tighter routine,
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;; so that we don't have timing problems, as the requirements
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;; are quite tight. Basically we need to read the clock and data
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;; bit from the same byte read.
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; ;; Wait for CLK to release
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; ;; jsr iec_wait_for_clock_release
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; ;; (we do this implicitly below, with a tighter routine,
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; ;; so that we don't have timing problems, as the requirements
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; ;; are quite tight. Basically we need to read the clock and data
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; ;; bit from the same byte read.
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;; DATA now has the next bit, but inverted (well, except that it turns out not to be).
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;; DATA is in bit7, which is a bit annoying.
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;; But we can clock it out with a ROL instruction
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;; so that it is in C. We can then ROR it into the
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;; partial data byte.
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;; We use ROR so that we shift in from the top, so that
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;; the first bit we shift in ends up in bit 0 after all
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;; 8 bits have been read.
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;; ODD: For some reason we don't need to invert the
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;; received bits. This is weird, because we invert them
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;; on the way out, and everything in the protocol seems
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;; to indicate that we sould do so. But experimentation
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;; has confirmed the bits don't need inversion on reception.
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;; Move data bit into C flag, and loop until bit 6 clears
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;; i.e., the clock has been released.
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* LDA $DD00
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ROL
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bpl -
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;; Pull it into the data byte
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pla
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ROR
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pha
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; ;; DATA now has the next bit, but inverted (well, except that it turns out not to be).
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; ;; DATA is in bit7, which is a bit annoying.
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; ;; But we can clock it out with a ROL instruction
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; ;; so that it is in C. We can then ROR it into the
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; ;; partial data byte.
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; ;; We use ROR so that we shift in from the top, so that
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; ;; the first bit we shift in ends up in bit 0 after all
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; ;; 8 bits have been read.
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; ;; ODD: For some reason we don't need to invert the
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; ;; received bits. This is weird, because we invert them
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; ;; on the way out, and everything in the protocol seems
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; ;; to indicate that we sould do so. But experimentation
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; ;; has confirmed the bits don't need inversion on reception.
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;; Wait for CLK to re-assert
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jsr iec_wait_for_clock_assert
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; ;; Move data bit into C flag, and loop until bit 6 clears
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; ;; i.e., the clock has been released.
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;* LDA $DD00
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; ROL
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; bpl -
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;; More bits?
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dex
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bpl iec_rx_bit_loop
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; ;; Pull it into the data byte
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;; pla
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; ROR
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; pha
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;; Then we must within 1000usec acknowledge the frame by
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;; asserting DATA. At this point, CLK is asserted by the
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;; talker and DATA by us, i.e., we are ready to receive
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;; the next byte. (p11).
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jsr iec_assert_data
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; ;; Wait for CLK to re-assert
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; jsr iec_wait_for_clock_assert
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;; Retreive the received byte
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PLA
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; ;; More bits?
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; dex
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; bpl iec_rx_bit_loop
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; ;; Then we must within 1000usec acknowledge the frame by
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; ;; asserting DATA. At this point, CLK is asserted by the
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; ;; talker and DATA by us, i.e., we are ready to receive
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; ;; the next byte. (p11).
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; jsr iec_assert_data
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; ;; Retreive the received byte
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; PLA
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; ;; Return no-error
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; CLC
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; RTS
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;; Return no-error
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CLC
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RTS
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@@ -0,0 +1,7 @@
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iec_set_idle:
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lda CI2PRA
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ora #BIT_CI2PRA_CLK_OUT ; pull
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and #$FF - BIT_CI2PRA_DAT_OUT - BIT_CI2PRA_ATN_OUT ; release
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sta CI2PRA
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rts
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@@ -1,87 +1,10 @@
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iec_tx_byte:
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;; Implemented based on https://www.pagetable.com/?p=1135, https://github.com/mist64/cbmbus_doc
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iec_tx_byte:
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pha
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jsr iec_assert_clk_release_data
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;; Give devices time to respond
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jsr wait1ms
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;; Did a device respond? (DATA will be pulled if so)
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lda $DD00
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bpl +
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;; No devices present, so we can immediately return with device not found
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pla
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jmp kernalerror_DEVICE_NOT_FOUND
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*
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;; Release CLK and wait for DATA to release.
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jsr iec_release_clk_and_data
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;; Wait for DATA to be released
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;; Listener is allowed to hold DATA for as long as they want.
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;; i.e., this is the part of the protocol where the listener indicates
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;; that they are busy doing something, like processing the previous
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;; character.
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jsr iec_wait_for_data_release
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;; We then wait for 60 usec (less than 200usec so we don't
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;; signal EOI), before asserting CLK again.
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jsr iec_wait60us
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;; Do the actual transmission of 8 bits of data
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ldx #7
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pla
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iec_tx_byte_nextbit:
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;; Is next bit 0 or 1?
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lsr
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pha
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bcs +
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;; Setup 0
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jsr iec_assert_clk_and_data
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jmp iec_tx_byte_l1
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*
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;; Setup 1
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jsr iec_assert_clk_release_data
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iec_tx_byte_l1:
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;; Clock bit out
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jsr iec_wait20us
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jsr iec_release_clk
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jsr iec_wait20us
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;; More bits to send?
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pla
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dex
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bpl iec_tx_byte_nextbit
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;; Done sending bits. Assert CLK and wait for acknowledgement
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jsr iec_assert_clk_release_data
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;; Acknowledgement must happen within 1ms, else it
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;; is DEVICE NOT PRESENT
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;; Acknowledgement consists of the DATA line being pulled
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;; by the listener.
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;; We can't easily count rasters here, so we just
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;; try a set number of times
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ldx #$ff
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* lda $DD00
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;; BPL here is checking that bit 7 of $DD00 clears,
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;; i.e, that the DATA line is asserted.
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bpl +
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dex
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bne -
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;; Timeout - DEVICE NOT PRESENT
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jmp kernalerror_DEVICE_NOT_FOUND
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*
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;; All done.
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;; End state is TALKER is asserting CLK, and listener is asserting DATA
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;; until they are ready for the next byte.
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clc
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;; XXX to be filled-in
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rts
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+12
-69
@@ -1,63 +1,5 @@
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;; XXX - TEMPORARY IMPLEMENTATION
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;; https://www.pagetable.com/?p=1135, https://github.com/mist64/cbmbus_doc
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;; https://www.c64-wiki.com/wiki/CIA#CIA_2
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.alias CI2PRA $DD00
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.alias BIT_IEC_ATN_OUT $08 ; 1 - low (pulled), 0 - high (released)
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.alias BIT_IEC_CLK_OUT $10 ; 1 - low (pulled), 0 - high (released)
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.alias BIT_IEC_DAT_OUT $20 ; 1 - low (pulled), 0 - high (released)
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.alias BIT_IEC_CLK_IN $40 ; 0 - low (pulled), 1 - high (released)
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.alias BIT_IEC_DAT_IN $80 ; 0 - low (pulled), 1 - high (released)
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; XXX optimize these below
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xxx_to_idle_state:
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lda CI2PRA
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ora #BIT_IEC_CLK_OUT ; pull
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and #$FF - BIT_IEC_DAT_OUT - BIT_IEC_ATN_OUT ; release
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sta CI2PRA
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rts
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xxx_pull_atn_clk_release_data:
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lda CI2PRA
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ora #BIT_IEC_ATN_OUT + BIT_IEC_CLK_OUT ; pull
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and #$FF - BIT_IEC_DAT_OUT ; release
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sta CI2PRA
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rts
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xxx_pull_clk_release_data:
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lda CI2PRA
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ora #BIT_IEC_CLK_OUT ; pull
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and #$FF - BIT_IEC_DAT_OUT ; release
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sta CI2PRA
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rts
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xxx_release_clk_data:
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lda CI2PRA
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and #$FF - BIT_IEC_CLK_OUT - BIT_IEC_DAT_OUT ; release
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sta CI2PRA
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rts
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xxx_release_clk_pull_data:
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lda CI2PRA
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and #$FF - BIT_IEC_CLK_OUT ; release
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ora #BIT_IEC_DAT_OUT ; pull
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sta CI2PRA
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rts
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xxx_wait_for_data_release:
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lda CI2PRA
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;; Check the highest bit, which is DATA IN,
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;; (highest bit set = negative value)
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bpl xxx_wait_for_data_release
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rts
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||||
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;; Implemented based on https://www.pagetable.com/?p=1135, https://github.com/mist64/cbmbus_doc
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iec_tx_command:
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@@ -65,14 +7,14 @@ iec_tx_command:
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;; Notify all devices that we are going to send a byte
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;; and it is going to be a command (pulled ATN)
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||||
jsr xxx_pull_atn_clk_release_data
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jsr iec_pull_atn_clk_release_data
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;; Give devices time to respond (response is mandatory!)
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jsr wait1ms
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;; Did at least one device respond by pulling DATA?
|
||||
lda CI2PRA
|
||||
and #BIT_IEC_DAT_IN
|
||||
and #BIT_CI2PRA_DAT_IN
|
||||
beq +
|
||||
|
||||
;; No devices present on the bus, so we can immediately return with device not found
|
||||
@@ -81,7 +23,7 @@ iec_tx_command:
|
||||
jsr printf
|
||||
.byte "DBG: NO DEVICES AT ALL", $0D, 0
|
||||
|
||||
jsr xxx_to_idle_state
|
||||
jsr iec_set_idle
|
||||
jmp kernalerror_DEVICE_NOT_FOUND
|
||||
*
|
||||
;; At least one device responded, but they are still allowed to stall
|
||||
@@ -90,13 +32,13 @@ iec_tx_command:
|
||||
;; - release back CLK, keep DATA released
|
||||
;; - afterwards wait till all devices also release DATA
|
||||
|
||||
jsr xxx_release_clk_data
|
||||
jsr xxx_wait_for_data_release
|
||||
jsr iec_release_clk_data
|
||||
jsr iec_wait_for_data_release
|
||||
|
||||
;; Pull CLK back to indicate that DATA is not valid, keep it for 60us
|
||||
;; Don't wait too long, as 200us or more is considered EOI
|
||||
|
||||
jsr xxx_pull_clk_release_data
|
||||
jsr iec_pull_clk_release_data
|
||||
jsr iec_wait60us
|
||||
|
||||
;; Now, we can start transmission of 8 bits of data
|
||||
@@ -110,11 +52,11 @@ iec_tx_command_nextbit:
|
||||
bcs +
|
||||
|
||||
;; Bit is 0
|
||||
jsr xxx_release_clk_pull_data
|
||||
jsr iec_release_clk_pull_data
|
||||
jmp iec_tx_command_bitset
|
||||
*
|
||||
;; Bit is 1
|
||||
jsr xxx_release_clk_data
|
||||
jsr iec_release_clk_data
|
||||
|
||||
iec_tx_command_bitset:
|
||||
|
||||
@@ -122,7 +64,7 @@ iec_tx_command_bitset:
|
||||
jsr iec_wait20us
|
||||
|
||||
;; Pull CLK for 20us again
|
||||
jsr xxx_pull_clk_release_data
|
||||
jsr iec_pull_clk_release_data
|
||||
jsr iec_wait20us
|
||||
|
||||
;; More bits to send?
|
||||
@@ -145,7 +87,8 @@ iec_tx_command_bitset:
|
||||
bne -
|
||||
bpl iec_tx_command_done
|
||||
*
|
||||
;; XXX wait 100ms
|
||||
;; Wait 100us to give busy devices some time
|
||||
jsr iec_wait100us
|
||||
|
||||
iec_tx_command_done:
|
||||
|
||||
|
||||
@@ -0,0 +1,25 @@
|
||||
|
||||
iec_wait100us:
|
||||
|
||||
;; Wait 100usec
|
||||
|
||||
;; PAL:
|
||||
;; - CPU frequency 0.985248 MHz, we need to waste at least 102 cycles
|
||||
;; NTSC:
|
||||
;; - CPU frequency 1.022727 MHZ, we need to waste at least 98 cycles
|
||||
|
||||
;; Waste cycles by reading some unimportant memory location
|
||||
;; (in a loop) in order not to clutter VICE debug logs
|
||||
|
||||
;; Waste cycles in a loop
|
||||
|
||||
ldy #$12 ; 2 cycles
|
||||
* dey ; 2 cycles * 18
|
||||
bpl - ; 3 cycles * 17 + 2 cycles
|
||||
rts ; 6 cycles
|
||||
|
||||
;; 6 cycles JSR to routine,
|
||||
;; 97 cycles routine with RTS
|
||||
;; 1 cycle to fetch next instruction
|
||||
;; ---
|
||||
;; 104 cycles
|
||||
@@ -1,7 +1,22 @@
|
||||
|
||||
iec_wait20us:
|
||||
iec_wait20us:
|
||||
|
||||
;; Wait 20usec
|
||||
;; JSR + RTS already costs 12, so need only 8 more
|
||||
ldy $dd01 ; reading dd00 makes debugging harder
|
||||
ldy $dd01
|
||||
rts
|
||||
|
||||
;; PAL:
|
||||
;; - CPU frequency 0.985248 MHz, we need to waste at least 21 cycles
|
||||
;; NTSC:
|
||||
;; - CPU frequency 1.022727 MHZ, we need to waste at least 20 cycles
|
||||
|
||||
;; Waste cycles by reading some unimportant memory location
|
||||
;; in order not to clutter VICE debug logs
|
||||
|
||||
ora $03FF ; 4 cycles
|
||||
ora $03FF ; 4 cycles
|
||||
rts ; 6 cycles
|
||||
|
||||
;; 6 cycles JSR to routine,
|
||||
;; 14 cycles routine with RTS
|
||||
;; 1 cycle to fetch next instruction
|
||||
;; ---
|
||||
;; 21 cycles
|
||||
@@ -1,9 +1,23 @@
|
||||
iec_wait60us:
|
||||
|
||||
;; Waste ~60 clock cycles (including JSR + RTS)
|
||||
ldy #$06
|
||||
* lda $dd01 ; reading dd00 makes debugging harder
|
||||
dey
|
||||
bpl -
|
||||
iec_wait60us:
|
||||
|
||||
;; Wait 60usec
|
||||
|
||||
;; PAL:
|
||||
;; - CPU frequency 0.985248 MHz, we need to waste at least 61 cycles
|
||||
;; NTSC:
|
||||
;; - CPU frequency 1.022727 MHZ, we need to waste at least 59 cycles
|
||||
|
||||
;; Waste cycles in a loop
|
||||
|
||||
ldy #$0A ; 2 cycles
|
||||
* dey ; 2 cycles * 10
|
||||
bpl - ; 3 cycles * 9 + 2 cycles
|
||||
rts ; 6 cycles
|
||||
|
||||
;; 6 cycles JSR to routine,
|
||||
;; 57 cycles routine with RTS
|
||||
;; 1 cycle to fetch next instruction
|
||||
;; ---
|
||||
;; 64 cycles
|
||||
|
||||
rts
|
||||
@@ -1,5 +0,0 @@
|
||||
iec_wait_for_clock_assert:
|
||||
LDA $DD00
|
||||
and #$40
|
||||
bne iec_wait_for_clock_assert
|
||||
rts
|
||||
@@ -1,5 +0,0 @@
|
||||
iec_wait_for_clock_release:
|
||||
LDA $DD00
|
||||
and #$40
|
||||
beq iec_wait_for_clock_release
|
||||
rts
|
||||
@@ -1,5 +1,7 @@
|
||||
|
||||
iec_wait_for_data_release:
|
||||
LDA $DD00
|
||||
and #$40
|
||||
beq iec_wait_for_data_release
|
||||
lda CI2PRA
|
||||
;; Check the highest bit, which is DATA IN,
|
||||
;; (highest bit set = negative value)
|
||||
bpl iec_wait_for_data_release
|
||||
rts
|
||||
+16
-25
@@ -14,6 +14,9 @@
|
||||
;; $93 = kernal_load_or_verify_flag
|
||||
;; $AC = current pointer for loading/verifying
|
||||
;; $C1 = similar to the above.
|
||||
|
||||
;; XXX rework this, according to pagetable.com
|
||||
|
||||
load:
|
||||
|
||||
;; Are we loading or verifying?
|
||||
@@ -47,17 +50,11 @@ print_filename_loop:
|
||||
lda #$0d
|
||||
jsr $ffd2
|
||||
|
||||
;; Begin sending under attention
|
||||
jsr iec_assert_atn
|
||||
|
||||
;; XXX - Use default device number
|
||||
;; http://www.zimmers.net/anonftp/pub/cbm/programming/serial-bus.pdf
|
||||
;; p13, 16.
|
||||
;; also p16 tells us this routine doesn't mess with the file table in the C64,
|
||||
;; only in the drive.
|
||||
|
||||
;; Begin sending under attention
|
||||
jsr iec_assert_atn
|
||||
|
||||
;; XXX - Use default device number
|
||||
;; http://www.zimmers.net/anonftp/pub/cbm/programming/serial-bus.pdf
|
||||
@@ -67,16 +64,15 @@ print_filename_loop:
|
||||
|
||||
;; Call device to LISTEN (p16)
|
||||
lda #$28
|
||||
jsr iec_tx_byte
|
||||
jsr iec_tx_command
|
||||
bcs load_error
|
||||
|
||||
;; Open channel #0 (p16)
|
||||
lda #$f0
|
||||
jsr iec_tx_byte
|
||||
jsr iec_tx_command
|
||||
bcs load_error
|
||||
|
||||
;; (p16)
|
||||
jsr iec_release_atn
|
||||
jsr iec_set_idle
|
||||
|
||||
;; Send filename (p16)
|
||||
ldy #0
|
||||
@@ -103,27 +99,24 @@ send_filename:
|
||||
|
||||
sent_filename:
|
||||
;; Command device to unlisten to indicate end of file name. (p16)
|
||||
jsr iec_assert_atn
|
||||
lda #$3f
|
||||
jsr iec_tx_byte
|
||||
jsr iec_tx_command
|
||||
bcs load_error
|
||||
jsr iec_release_atn
|
||||
jsr iec_set_idle
|
||||
|
||||
;; Now command device to talk (p16)
|
||||
jsr iec_assert_atn
|
||||
lda #$48
|
||||
jsr iec_tx_byte
|
||||
jsr iec_tx_command
|
||||
bcs load_error
|
||||
|
||||
lda #$60 ; open channel / data (p3) , required according to p13
|
||||
jsr iec_tx_byte
|
||||
jsr iec_tx_command
|
||||
bcs load_error
|
||||
jsr iec_release_atn
|
||||
|
||||
;; We are currently talker, so do the IEC turn around so that we
|
||||
;; are the listener (p16)
|
||||
;; An error here means FILE NOT FOUND ?
|
||||
jsr iec_turnaround_to_listen
|
||||
;; XXX jsr iec_turnaround_to_listen
|
||||
bcs load_error
|
||||
|
||||
;; Get load address and store it if secondary address is zero
|
||||
@@ -133,7 +126,7 @@ sent_filename:
|
||||
beq +
|
||||
sta load_save_start_ptr+0
|
||||
*
|
||||
jsr iec_rx_byte
|
||||
jsr iec_tx_command
|
||||
bcs file_not_found_error
|
||||
ldx current_secondary_address
|
||||
beq +
|
||||
@@ -178,17 +171,15 @@ load_done:
|
||||
;; Close file on drive
|
||||
|
||||
;; Command drive to stop talking and to close the file
|
||||
jsr iec_assert_atn
|
||||
lda #$5f
|
||||
jsr iec_tx_byte
|
||||
jsr iec_tx_command
|
||||
lda #$28
|
||||
jsr iec_tx_byte
|
||||
jsr iec_tx_command
|
||||
lda #$e0
|
||||
jsr iec_tx_byte
|
||||
jsr iec_tx_command
|
||||
;; Tell drive to unlisten
|
||||
lda #$3f
|
||||
jsr iec_tx_byte
|
||||
jsr iec_release_atn
|
||||
jsr iec_tx_command
|
||||
|
||||
;; Return last address written to +1
|
||||
;; (Even though Compute's Mapping the 64 says without the +1.
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
; Function defined on pp272-273 of C64 Programmers Reference Guide
|
||||
;; See also http://www.zimmers.net/anonftp/pub/cbm/programming/serial-bus.pdf
|
||||
|
||||
;; XXX rework this, according to pagetable.com
|
||||
|
||||
open:
|
||||
|
||||
|
||||
Reference in new issue
Block a user