more work on IEC, some refactoring and temporary breakage

2019-06-20 11:23:30 +02:00
1 parent fd04410bd8
commit edb0013536
@@ -117,3 +117,13 @@
 	.alias poke_under_roms tiny_nmi_handler+poke_under_roms_routine-tiny_nmi_handler_routine
 	.alias memmap_allram tiny_nmi_handler+memmap_allram_routine-tiny_nmi_handler_routine
 	.alias memmap_normal tiny_nmi_handler+memmap_normal_routine-tiny_nmi_handler_routine
 	;; CIA#2 - https://www.c64-wiki.com/wiki/CIA#CIA_2
 	.alias CI2PRA $DD00 ; VIC bank switching and IEC port
 	.alias BIT_CI2PRA_ATN_OUT $08    ; 1 - low (pulled), 0 - high (released)
 	.alias BIT_CI2PRA_CLK_OUT $10    ; 1 - low (pulled), 0 - high (released)
 	.alias BIT_CI2PRA_DAT_OUT $20    ; 1 - low (pulled), 0 - high (released)
 	.alias BIT_CI2PRA_CLK_IN  $40    ; 0 - low (pulled), 1 - high (released)
 	.alias BIT_CI2PRA_DAT_IN  $80    ; 0 - low (pulled), 1 - high (released)
@@ -39,4 +39,7 @@ ioinit:
 	lda #$3b
 	sta $dd02
 	;; Set IEC bus oto its initial idle state
 	jsr iec_set_idle
 	rts
@@ -1,5 +0,0 @@
 iec_assert_atn:
 	lda $dd00
 	ora #$08
 	sta $dd00
 	rts
@@ -1,6 +0,0 @@
 iec_assert_clk_and_data:
 	lda $dd00
 	and #$0b
 	ora #$30
 	sta $dd00
 	rts
@@ -1,6 +0,0 @@
 iec_assert_clk_release_data:
 	lda $dd00
 	and #$0b
 	ora #$10
 	sta $dd00
 	rts
@@ -1,5 +0,0 @@
 iec_assert_data:
 	lda $dd00
 	ora #$20
 	sta $dd00
 	rts
@@ -0,0 +1,7 @@
 iec_pull_atn_clk_release_data:
 	lda CI2PRA
 	ora #BIT_CI2PRA_ATN_OUT + BIT_CI2PRA_CLK_OUT    ; pull
 	and #$FF - BIT_CI2PRA_DAT_OUT                   ; release
 	sta CI2PRA
 	rts
@@ -0,0 +1,7 @@
 iec_pull_clk_release_data:
 	lda CI2PRA
 	ora #BIT_CI2PRA_CLK_OUT          ; pull
 	and #$FF - BIT_CI2PRA_DAT_OUT    ; release
 	sta CI2PRA
 	rts
@@ -1,11 +0,0 @@
 iec_release_atn:
 	lda $dd00
 	and #$f7
 	sta $dd00
 	;; Also clear EOI marker
 	lda IOSTATUS
 	and #$bf
 	sta IOSTATUS
 	rts
@@ -1,5 +0,0 @@
 iec_release_clk:
 	lda $dd00
 	and #$2b
 	sta $dd00
 	rts
@@ -1,6 +0,0 @@
 iec_release_clk_and_data:	
 	lda $DD00
 	and #$0b
 	sta $DD00
 	rts
@@ -0,0 +1,6 @@
 iec_release_clk_data:
 	lda CI2PRA
 	and #$FF - BIT_CI2PRA_CLK_OUT - BIT_CI2PRA_DAT_OUT    ; release
 	sta CI2PRA
 	rts
@@ -0,0 +1,7 @@
 iec_release_clk_pull_data:
 	lda CI2PRA
 	and #$FF - BIT_CI2PRA_CLK_OUT    ; release
 	ora #BIT_CI2PRA_DAT_OUT          ; pull
 	sta CI2PRA
 	rts
@@ -3,112 +3,116 @@
 	;; page 11.
 ;; XXX rework this, according to pagetable.com
 iec_rx_byte:
 	;; First, we wait for the talker to release the CLK line.
 	jsr iec_wait_for_clock_release
 	;; We then release the data line
 	;; (We can use this routine, since we weren't holding CLK, anyway)
 	jsr iec_release_clk_and_data
 	;; Wait for talker to assert CLK.
 	;; If >200usec, then it is EOI and we have to assert the
 	;; DATA line for 60 usec to tell the TALKER that we have
 	;; acknowledged the EOI.
 	ldx #20
 iec_rx_clk_wait:
 	;; Loop takes 11 usec, so ~20 iterations for 200usec timeout
 	lda $dd00
 	rol
 	bpl not_eoi
 	dex
 	cpx #$21
 	bne not_rx_timeout
 	;; Time out waiting for CLK to assert again.
 	;;  = error
 	sec
 	rts
 ;	;; First, we wait for the talker to release the CLK line.
 ;	;; XXX jsr iec_wait_for_clock_release
 ;	;; We then release the data line
 ;	;; (We can use this routine, since we weren't holding CLK, anyway)
 ;	jsr iec_release_clk_and_data
 ;	;; Wait for talker to assert CLK.
 ;	;; If >200usec, then it is EOI and we have to assert the
 ;	;; DATA line for 60 usec to tell the TALKER that we have
 ;	;; acknowledged the EOI.
 ;	ldx #20
 iec_rx_clk_wait:
 ;	;; Loop takes 11 usec, so ~20 iterations for 200usec timeout
 ;	lda $dd00
 ;	rol
 ;	bpl not_eoi
 ;	dex
 ;	cpx #$21
 ;	bne not_rx_timeout
 ;	;; Time out waiting for CLK to assert again.
 ;	;;  = error
 ;	sec
 ;	rts
 not_rx_timeout:
-	cpx #$00
+;	cpx #$00
-	bpl iec_rx_clk_wait
+;	bpl iec_rx_clk_wait
-	;; Remember EOI condition
+;	;; Remember EOI condition
-	lda IOSTATUS
+;	lda IOSTATUS
-	ora #$40
+;	ora #$40
-	sta IOSTATUS
+;	sta IOSTATUS
-	;; EOI timeout: So pulse DATA line for 60 usec
+;	;; EOI timeout: So pulse DATA line for 60 usec
-	jsr iec_assert_data
+;	jsr iec_assert_data
-	jsr iec_wait60us
+;	jsr iec_wait60us
-	jsr iec_release_clk_and_data
+;	jsr iec_release_clk_and_data
-	;; And still wait for CLK to be asserted
+;	;; And still wait for CLK to be asserted
-	;; XXX - This will cause periodic EOI pulses if the sender takes too long.
+;	;; XXX - This will cause periodic EOI pulses if the sender takes too long.
-	;; That is probably ok.
+;	;; That is probably ok.
-	ldx #$7f
+;	ldx #$7f
-	jmp iec_rx_clk_wait
+;	jmp iec_rx_clk_wait
 not_eoi:
-	;; CLK is now low.  Latch input bits in on rising edge
+;	;; CLK is now low.  Latch input bits in on rising edge
-	;; of CLK, eight times for eight bits.
+;	;; of CLK, eight times for eight bits.
-	ldx #7
+;	ldx #7
-	;; Get empty byte to load into.
+;	;; Get empty byte to load into.
-	lda #$00
+;	lda #$00
-	pha
+;	pha
 iec_rx_bit_loop:
-	;; Wait for CLK to release
+;	;; Wait for CLK to release
-	;; jsr iec_wait_for_clock_release
+;	;; jsr iec_wait_for_clock_release
-	;; (we do this implicitly below, with a tighter routine,
+;	;; (we do this implicitly below, with a tighter routine,
-	;; so that we don't have timing problems, as the requirements
+;	;; so that we don't have timing problems, as the requirements
-	;; are quite tight. Basically we need to read the clock and data
+;	;; are quite tight. Basically we need to read the clock and data
-	;; bit from the same byte read.
+;	;; bit from the same byte read.
-	;; DATA now has the next bit, but inverted (well, except that it turns out not to be).
+;	;; DATA now has the next bit, but inverted (well, except that it turns out not to be).
-	;; DATA is in bit7, which is a bit annoying.
+;	;; DATA is in bit7, which is a bit annoying.
-	;; But we can clock it out with a ROL instruction
+;	;; But we can clock it out with a ROL instruction
-	;; so that it is in C. We can then ROR it into the
+;	;; so that it is in C. We can then ROR it into the
-	;; partial data byte.
+;	;; partial data byte.
-	;; We use ROR so that we shift in from the top, so that
+;	;; We use ROR so that we shift in from the top, so that
-	;; the first bit we shift in ends up in bit 0 after all
+;	;; the first bit we shift in ends up in bit 0 after all
-	;; 8 bits have been read.
+;	;; 8 bits have been read.
-	;; ODD: For some reason we don't need to invert the
+;	;; ODD: For some reason we don't need to invert the
-	;; received bits.  This is weird, because we invert them
+;	;; received bits.  This is weird, because we invert them
-	;; on the way out, and everything in the protocol seems
+;	;; on the way out, and everything in the protocol seems
-	;; to indicate that we sould do so.  But experimentation
+;	;; to indicate that we sould do so.  But experimentation
-	;; has confirmed the bits don't need inversion on reception.
+;	;; has confirmed the bits don't need inversion on reception.
-	;; Move data bit into C flag, and loop until bit 6 clears
+;	;; Move data bit into C flag, and loop until bit 6 clears
-	;; i.e., the clock has been released.
+;	;; i.e., the clock has been released.
-*	LDA $DD00
+;*	LDA $DD00
-	ROL
+;	ROL
-	bpl -
+;	bpl -
-	;; Pull it into the data byte
+;	;; Pull it into the data byte
-	pla
+;;	pla
-	ROR
+;	ROR
-	pha
+;	pha
-	;; Wait for CLK to re-assert
+;	;; Wait for CLK to re-assert
-	jsr iec_wait_for_clock_assert
+;	jsr iec_wait_for_clock_assert
-	;; More bits?
+;	;; More bits?
-	dex
+;	dex
-	bpl iec_rx_bit_loop
+;	bpl iec_rx_bit_loop
-	;; Then we must within 1000usec acknowledge the frame by
+;	;; Then we must within 1000usec acknowledge the frame by
-	;; asserting DATA. At this point, CLK is asserted by the
+;	;; asserting DATA. At this point, CLK is asserted by the
-	;; talker and DATA by us, i.e., we are ready to receive
+;	;; talker and DATA by us, i.e., we are ready to receive
-	;; the next byte. (p11).
+;	;; the next byte. (p11).
-	jsr iec_assert_data
+;	jsr iec_assert_data
-	;; Retreive the received byte
+;	;; Retreive the received byte
-	PLA
+;	PLA
-	;; Return no-error
+;	;; Return no-error
-	CLC
+;	CLC
-	RTS
+;	RTS
@@ -0,0 +1,7 @@
 iec_set_idle:
 	lda CI2PRA
 	ora #BIT_CI2PRA_CLK_OUT                               ; pull
 	and #$FF - BIT_CI2PRA_DAT_OUT - BIT_CI2PRA_ATN_OUT    ; release
 	sta CI2PRA
 	rts
@@ -1,87 +1,10 @@
 ;; Implemented based on https://www.pagetable.com/?p=1135, https://github.com/mist64/cbmbus_doc
 iec_tx_byte:
 	pha
-	jsr iec_assert_clk_release_data
+;; XXX to be filled-in
 	;; Give devices time to respond
 	jsr wait1ms
 	;; Did a device respond? (DATA will be pulled if so)
 	lda $DD00
 	bpl +
 	;; No devices present, so we can immediately return with device not found
 	pla
 	jmp kernalerror_DEVICE_NOT_FOUND
 *
 	;; Release CLK and wait for DATA to release.
 	jsr iec_release_clk_and_data
 	;; Wait for DATA to be released
 	;; Listener is allowed to hold DATA for as long as they want.
 	;; i.e., this is the part of the protocol where the listener indicates
 	;; that they are busy doing something, like processing the previous
 	;; character.
 	jsr iec_wait_for_data_release
 	;; We then wait for 60 usec (less than 200usec so we don't
 	;; signal EOI), before asserting CLK again.
 	jsr iec_wait60us
 	;; Do the actual transmission of 8 bits of data
 	ldx #7
 	pla
 iec_tx_byte_nextbit:	
 	;; Is next bit 0 or 1?
 	lsr
 	pha
 	bcs +
 	;; Setup 0
 	jsr iec_assert_clk_and_data
 	jmp iec_tx_byte_l1
 *
 	;; Setup 1
 	jsr iec_assert_clk_release_data
 iec_tx_byte_l1:
 	;; Clock bit out
 	jsr iec_wait20us
 	jsr iec_release_clk
 	jsr iec_wait20us
 	;; More bits to send?
 	pla
 	dex
 	bpl iec_tx_byte_nextbit
 	;; Done sending bits. Assert CLK and wait for acknowledgement
 	jsr iec_assert_clk_release_data
 	;; Acknowledgement must happen within 1ms, else it
 	;; is DEVICE NOT PRESENT
 	;; Acknowledgement consists of the DATA line being pulled
 	;; by the listener.
 	;; We can't easily count rasters here, so we just
 	;; try a set number of times
 	ldx #$ff
 *	lda $DD00
 	;; BPL here is checking that bit 7 of $DD00 clears,
 	;; i.e, that the DATA line is asserted.
 	bpl +
 	dex
 	bne -
 	;; Timeout - DEVICE NOT PRESENT
 	jmp kernalerror_DEVICE_NOT_FOUND
 *
 	;; All done.
 	;; End state is TALKER is asserting CLK, and listener is asserting DATA
 	;; until they are ready for the next byte.
 	clc
 	rts
@@ -1,63 +1,5 @@
-
+;; Implemented based on https://www.pagetable.com/?p=1135, https://github.com/mist64/cbmbus_doc
 ;; XXX - TEMPORARY IMPLEMENTATION
 ;; https://www.pagetable.com/?p=1135, https://github.com/mist64/cbmbus_doc
 ;; https://www.c64-wiki.com/wiki/CIA#CIA_2
 .alias CI2PRA $DD00
 .alias BIT_IEC_ATN_OUT $08    ; 1 - low (pulled), 0 - high (released)
 .alias BIT_IEC_CLK_OUT $10    ; 1 - low (pulled), 0 - high (released)
 .alias BIT_IEC_DAT_OUT $20    ; 1 - low (pulled), 0 - high (released)
 .alias BIT_IEC_CLK_IN  $40    ; 0 - low (pulled), 1 - high (released)
 .alias BIT_IEC_DAT_IN  $80    ; 0 - low (pulled), 1 - high (released)
 ; XXX optimize these below
 xxx_to_idle_state:
 	lda CI2PRA
 	ora #BIT_IEC_CLK_OUT                            ; pull
 	and #$FF - BIT_IEC_DAT_OUT - BIT_IEC_ATN_OUT    ; release
 	sta CI2PRA
 	rts
 xxx_pull_atn_clk_release_data:
 	lda CI2PRA
 	ora #BIT_IEC_ATN_OUT + BIT_IEC_CLK_OUT    ; pull
 	and #$FF - BIT_IEC_DAT_OUT                ; release
 	sta CI2PRA
 	rts
 xxx_pull_clk_release_data:
 	lda CI2PRA
 	ora #BIT_IEC_CLK_OUT          ; pull
 	and #$FF - BIT_IEC_DAT_OUT    ; release
 	sta CI2PRA
 	rts
 xxx_release_clk_data:
 	lda CI2PRA
 	and #$FF - BIT_IEC_CLK_OUT - BIT_IEC_DAT_OUT    ; release
 	sta CI2PRA
 	rts
 xxx_release_clk_pull_data:
 	lda CI2PRA
 	and #$FF - BIT_IEC_CLK_OUT    ; release
 	ora #BIT_IEC_DAT_OUT          ; pull
 	sta CI2PRA
 	rts
 xxx_wait_for_data_release:
 	lda CI2PRA
 	;; Check the highest bit, which is DATA IN,
 	;; (highest bit set = negative value)
 	bpl xxx_wait_for_data_release
 	rts
 iec_tx_command:
@@ -65,14 +7,14 @@ iec_tx_command:
 	;; Notify all devices that we are going to send a byte
 	;; and it is going to be a command (pulled ATN)
-	jsr xxx_pull_atn_clk_release_data
+	jsr iec_pull_atn_clk_release_data
 	;; Give devices time to respond (response is mandatory!)
 	jsr wait1ms
 	;; Did at least one device respond by pulling DATA?
 	lda CI2PRA
-	and #BIT_IEC_DAT_IN
+	and #BIT_CI2PRA_DAT_IN
 	beq +
 	;; No devices present on the bus, so we can immediately return with device not found
@@ -81,7 +23,7 @@ iec_tx_command:
 	jsr printf
 	.byte "DBG: NO DEVICES AT ALL", $0D, 0
-	jsr xxx_to_idle_state
+	jsr iec_set_idle
 	jmp kernalerror_DEVICE_NOT_FOUND
 *
 	;; At least one device responded, but they are still allowed to stall
@@ -90,13 +32,13 @@ iec_tx_command:
 	;; - release back CLK, keep DATA released
 	;; - afterwards wait till all devices also release DATA
-	jsr xxx_release_clk_data
+	jsr iec_release_clk_data
-	jsr xxx_wait_for_data_release
+	jsr iec_wait_for_data_release
 	;; Pull CLK back to indicate that DATA is not valid, keep it for 60us
 	;; Don't wait too long, as 200us or more is considered EOI
-	jsr xxx_pull_clk_release_data
+	jsr iec_pull_clk_release_data
 	jsr iec_wait60us
 	;; Now, we can start transmission of 8 bits of data
@@ -110,11 +52,11 @@ iec_tx_command_nextbit:
 	bcs +
 	;; Bit is 0
-	jsr xxx_release_clk_pull_data
+	jsr iec_release_clk_pull_data
 	jmp iec_tx_command_bitset
 *
 	;; Bit is 1
-	jsr xxx_release_clk_data
+	jsr iec_release_clk_data
 iec_tx_command_bitset:
@@ -122,7 +64,7 @@ iec_tx_command_bitset:
 	jsr iec_wait20us
 	;; Pull CLK for 20us again
-	jsr xxx_pull_clk_release_data
+	jsr iec_pull_clk_release_data
 	jsr iec_wait20us
 	;; More bits to send?
@@ -145,7 +87,8 @@ iec_tx_command_bitset:
 	bne -
 	bpl iec_tx_command_done
 *
-	;; XXX wait 100ms
+	;; Wait 100us to give busy devices some time
 	jsr iec_wait100us
 iec_tx_command_done:
@@ -0,0 +1,25 @@
 iec_wait100us:	
 	;; Wait 100usec
 	;; PAL:
 	;; - CPU frequency 0.985248 MHz, we need to waste at least 102 cycles
 	;; NTSC:
 	;; - CPU frequency 1.022727 MHZ, we need to waste at least 98 cycles
 	;; Waste cycles by reading some unimportant memory location
 	;; (in a loop) in order not to clutter VICE debug logs
 	;; Waste cycles in a loop
 	ldy #$12   ; 2 cycles
 *	dey        ; 2 cycles * 18
 	bpl -      ; 3 cycles * 17 + 2 cycles
 	rts        ; 6 cycles
 	;;   6 cycles JSR to routine, 
    ;;  97 cycles routine with RTS
    ;;   1 cycle to fetch next instruction
    ;; ---
    ;;  104 cycles
@@ -1,7 +1,22 @@
 iec_wait20us:
 	;; Wait 20usec
-	;; JSR + RTS already costs 12, so need only 8 more
+
-	ldy $dd01 ; reading dd00 makes debugging harder
+	;; PAL:
-	ldy $dd01
+	;; - CPU frequency 0.985248 MHz, we need to waste at least 21 cycles
-	rts
+	;; NTSC:
 	;; - CPU frequency 1.022727 MHZ, we need to waste at least 20 cycles
 	;; Waste cycles by reading some unimportant memory location
 	;; in order not to clutter VICE debug logs
 	ora $03FF    ; 4 cycles
 	ora $03FF    ; 4 cycles
 	rts          ; 6 cycles
 	;;   6 cycles JSR to routine, 
    ;;  14 cycles routine with RTS
    ;;   1 cycle to fetch next instruction
    ;; ---
    ;;  21 cycles
@@ -1,9 +1,23 @@
 iec_wait60us:
-	;; Waste ~60 clock cycles (including JSR + RTS)
+	;; Wait 60usec
-	ldy #$06
+
-*	lda $dd01 ; reading dd00 makes debugging harder
+	;; PAL:
-	dey
+	;; - CPU frequency 0.985248 MHz, we need to waste at least 61 cycles
-	bpl -
+	;; NTSC:
 	;; - CPU frequency 1.022727 MHZ, we need to waste at least 59 cycles
 	;; Waste cycles in a loop
 	ldy #$0A   ; 2 cycles
 *	dey        ; 2 cycles * 10
 	bpl -      ; 3 cycles * 9  + 2 cycles
 	rts        ; 6 cycles
 	;;   6 cycles JSR to routine, 
    ;;  57 cycles routine with RTS
    ;;   1 cycle to fetch next instruction
    ;; ---
    ;;  64 cycles
 	rts
@@ -1,5 +0,0 @@
 iec_wait_for_clock_assert:
 	LDA $DD00
 	and #$40
 	bne iec_wait_for_clock_assert
 	rts
@@ -1,5 +0,0 @@
 iec_wait_for_clock_release:
 	LDA $DD00
 	and #$40
 	beq iec_wait_for_clock_release
 	rts
@@ -1,5 +1,7 @@
 iec_wait_for_data_release:
-	LDA $DD00
+	lda CI2PRA
-	and #$40
+	;; Check the highest bit, which is DATA IN,
-	beq iec_wait_for_data_release
+	;; (highest bit set = negative value)
 	bpl iec_wait_for_data_release
 	rts
@@ -14,6 +14,9 @@
 	;; $93 = kernal_load_or_verify_flag
 	;; $AC = current pointer for loading/verifying
 	;; $C1 = similar to the above.
 ;; XXX rework this, according to pagetable.com
 load:
 	;; Are we loading or verifying?
@@ -47,18 +50,12 @@ print_filename_loop:
 	lda #$0d
 	jsr $ffd2
 	;; Begin sending under attention
 	jsr iec_assert_atn
 	;; XXX - Use default device number
 	;; http://www.zimmers.net/anonftp/pub/cbm/programming/serial-bus.pdf
 	;; p13, 16.
 	;; also p16 tells us this routine doesn't mess with the file table in the C64,
 	;; only in the drive.
 	;; Begin sending under attention
 	jsr iec_assert_atn
 	;; XXX - Use default device number
 	;; http://www.zimmers.net/anonftp/pub/cbm/programming/serial-bus.pdf
 	;; p13, 16.
@@ -67,16 +64,15 @@ print_filename_loop:
 	;; Call device to LISTEN (p16)
 	lda #$28
-	jsr iec_tx_byte
+	jsr iec_tx_command
 	bcs load_error
 	;; Open channel #0 (p16)
 	lda #$f0
-	jsr iec_tx_byte
+	jsr iec_tx_command
 	bcs load_error
-	;; (p16)
+	jsr iec_set_idle
 	jsr iec_release_atn
 	;; Send filename (p16)
 	ldy #0
@@ -103,27 +99,24 @@ send_filename:
 sent_filename:	
 	;; Command device to unlisten to indicate end of file name. (p16)
 	jsr iec_assert_atn
 	lda #$3f
-	jsr iec_tx_byte
+	jsr iec_tx_command
 	bcs load_error
-	jsr iec_release_atn
+	jsr iec_set_idle
 	;; Now command device to talk (p16)
 	jsr iec_assert_atn
 	lda #$48
-	jsr iec_tx_byte
+	jsr iec_tx_command
 	bcs load_error
 	lda #$60 ; open channel / data (p3) , required according to p13
-	jsr iec_tx_byte
+	jsr iec_tx_command
 	bcs load_error
 	jsr iec_release_atn
 	;; We are currently talker, so do the IEC turn around so that we
 	;; are the listener (p16)
 	;; An error here means FILE NOT FOUND ?
-	jsr iec_turnaround_to_listen
+	;; XXX jsr iec_turnaround_to_listen
 	bcs load_error
 	;; Get load address and store it if secondary address is zero
@@ -133,7 +126,7 @@ sent_filename:
 	beq +
 	sta load_save_start_ptr+0
 *
-	jsr iec_rx_byte
+	jsr iec_tx_command
 	bcs file_not_found_error
 	ldx current_secondary_address
 	beq +
@@ -178,17 +171,15 @@ load_done:
 	;; Close file on drive
 	;; Command drive to stop talking and to close the file
 	jsr iec_assert_atn
 	lda #$5f
-	jsr iec_tx_byte
+	jsr iec_tx_command
 	lda #$28
-	jsr iec_tx_byte
+	jsr iec_tx_command
 	lda #$e0
-	jsr iec_tx_byte
+	jsr iec_tx_command
 	;; Tell drive to unlisten
 	lda #$3f
-	jsr iec_tx_byte
+	jsr iec_tx_command
 	jsr iec_release_atn
 	;; Return last address written to +1
 	;; (Even though Compute's Mapping the 64 says without the +1.
@@ -1,6 +1,7 @@
 	; Function defined on pp272-273 of C64 Programmers Reference Guide
 	;; See also http://www.zimmers.net/anonftp/pub/cbm/programming/serial-bus.pdf
 ;; XXX rework this, according to pagetable.com
 open: