99 lines
2.1 KiB
ArmAsm
99 lines
2.1 KiB
ArmAsm
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;
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; Z80 instruction implementation - RR
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;
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!macro Z80_RR_REGn .REGn {
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clc
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bbr0 REG_F, @1
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sec
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@1:
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ror .REGn
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ldx .REGn
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bra Z80_common_RR
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}
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!macro Z80_RR_VIA_HL {
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jsr (VEC_fetch_via_HL)
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clc
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bbr0 REG_F, @1
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sec
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@1:
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ror
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sta [REG_HL],z
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bra Z80_common_RR_VIA
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}
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!macro Z80_RR_VIA_IXY_d {
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lda [PTR_IXY_d] ,z
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clc
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bbr0 REG_F, @1
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sec
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@1:
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ror
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; FALLTROUGH
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}
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!macro Z80_RR_VIA_IXY_d_REGn .REGn {
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lda [PTR_IXY_d] ,z
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clc
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bbr0 REG_F, @1
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sec
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@1:
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ror
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sta .REGn
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bra Z80_common_RR_VIA_IXY_d
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}
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Z80_instr_CB_18: +Z80_RR_REGn REG_B ; RR B
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Z80_instr_CB_19: +Z80_RR_REGn REG_C ; RR C
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Z80_instr_CB_1A: +Z80_RR_REGn REG_D ; RR D
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Z80_instr_CB_1B: +Z80_RR_REGn REG_E ; RR E
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Z80_instr_CB_1C: +Z80_RR_REGn REG_H ; RR H
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Z80_instr_CB_1D: +Z80_RR_REGn REG_L ; RR L
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Z80_instr_CB_1F: +Z80_RR_REGn REG_A ; RR A
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Z80_instr_CB_1E: +Z80_RR_VIA_HL ; RR (HL)
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Z80_instr_xDCB_1E: +Z80_RR_VIA_IXY_d ; RR (IXY+d)
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; FALLTROUGH
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Z80_common_RR_VIA_IXY_d:
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sta [PTR_IXY_d],z
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; FALLTROUGH
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Z80_common_RR_VIA:
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tax
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; FALLTROUGH
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Z80_common_RR:
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lda z80_ftable_IN_OR_XOR, x
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sta REG_F
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+bcc ZVM_next
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+Z80_PUT_1_CF
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jmp ZVM_next
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Z80_illeg_xDCB_18: +Z80_RR_VIA_IXY_d_REGn REG_B ; RR (IXY+d),B
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Z80_illeg_xDCB_19: +Z80_RR_VIA_IXY_d_REGn REG_C ; RR (IXY+d),C
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Z80_illeg_xDCB_1A: +Z80_RR_VIA_IXY_d_REGn REG_D ; RR (IXY+d),D
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Z80_illeg_xDCB_1B: +Z80_RR_VIA_IXY_d_REGn REG_E ; RR (IXY+d),E
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Z80_illeg_xDCB_1C: +Z80_RR_VIA_IXY_d_REGn REG_H ; RR (IXY+d),H
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Z80_illeg_xDCB_1D: +Z80_RR_VIA_IXY_d_REGn REG_L ; RR (IXY+d),L
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Z80_illeg_xDCB_1F: +Z80_RR_VIA_IXY_d_REGn REG_A ; RR (IXY+d),A
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