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more Z80 optimizations

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FeralChild64 authored and FeralChild64 committed 2021-01-26 00:03:07 +01:00
1 parent c9572d48df
commit d3b05ca2d6
17 files changed
+108 -162
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src/aliases/,aliases_ram_over64K_m65.s
+3 -3
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@@ -26,7 +26,7 @@
!set MEMCONF_SHADOW_BZP_3 = $00
; $1F800-$1FFFF (2KB) - color RAM mirror, not useable
; $20000-$4FFFF (64KB) - ROM, additions
; $20000-$3FFFF (64KB) - ROM, additions
; $50000-$57FFF (32KB) - reserved for graphics screen / Z80 memory bank 1
; $58000-... - native mode BASIC variables / Z80 memory bank 1 (up to $57FFF)
; $40000-$47FFF (32KB) - reserved for graphics screen / Z80 memory bank 0 ($40000-$4DFFF)
; $48000-... - native mode BASIC variables / Z80 memory bank 1 ($50000-$5FFFF)
src/zvm_m65/,aliases_zvm.s
+18 -20
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@@ -12,17 +12,17 @@
!addr REG_BC = $04 ; 2 bytes - combined register
!addr REG_C = REG_BC+0
!addr REG_B = REG_BC+1
!addr REG_BC_EXT1 = $06 ; 2 bytes - helper for faster access via BC in bank 1
!addr REG_BC_EXT = $06 ; 2 bytes - helper for faster access via BC in bank 1
!addr REG_DE = $08 ; 2 bytes - combined register
!addr REG_E = REG_DE+0
!addr REG_D = REG_DE+1
!addr REG_DE_EXT1 = $0A ; 2 bytes - helper for faster access via DE in bank 1
!addr REG_DE_EXT = $0A ; 2 bytes - helper for faster access via DE in bank 1
!addr REG_HL = $0C ; 2 bytes - combined register
!addr REG_L = REG_HL+0
!addr REG_H = REG_HL+1
!addr REG_HL_EXT1 = $0E ; 2 bytes - helper for faster access via HL in bank 1
!addr REG_HL_EXT = $0E ; 2 bytes - helper for faster access via HL in bank 1
!addr REG_SHADOW = $10 ; 8 bytes - shadow registers
!addr REG_F_SH = REG_SHADOW+0
@@ -35,9 +35,9 @@
!addr REG_H_SH = REG_SHADOW+7
!addr REG_SP = $18 ; 2 bytes - stack pointer
!addr REG_SP_EXT1 = $1A ; 2 bytes - helper for faster access via SP in bank 1
!addr REG_SP_EXT = $1A ; 2 bytes - helper for faster access via SP in bank 1
!addr REG_PC = $1C ; 2 bytes - sprogram counter
!addr REG_PC_EXT1 = $1E ; 2 bytes - helper for faster access via PC in bank 1
!addr REG_PC_EXT = $1E ; 2 bytes - helper for faster access via PC in bank 1
!addr REG_IX = $20 ; 2 bytes - index register
!addr REG_IXL = REG_IX+0
@@ -86,7 +86,7 @@
!addr zvm_bankvectors__start = $40
!addr VEC_fetch_via_PC_inc = $40 ; fetch to .A from (PC), increment PC afterwards
!addr VEC_fetch_stack = $42 ; fetch to .A - stack POP operation, destroys .X
!addr VEC_fetch_stack = $42 ; fetch to .A - stack POP operation
!addr VEC_store_stack = $44 ; store .A - stack PUSH operation, destroys .X
; XXX implement routines for vectors below
@@ -96,18 +96,17 @@
!addr VEC_fetch_via_DE = $4A
!addr VEC_store_via_DE = $4C
!addr VEC_fetch_via_HL = $4E
!addr VEC_fetch_via_HL_back = $50 ; forces PTR_DATA update
!addr VEC_store_via_HL = $52
!addr VEC_fetch_via_IX_d = $54
!addr VEC_fetch_via_IY_d = $56
!addr VEC_store_via_IX_d = $58
!addr VEC_store_via_IY_d = $5A
!addr VEC_fetch_via_nn = $5C
!addr VEC_store_via_nn = $5E
!addr VEC_fetch_via_plus1 = $60
!addr VEC_store_via_plus1 = $62 ; XXX jump to next directly?
!addr VEC_xchng_stack_lo = $64
!addr VEC_xchng_stack_hi = $68
!addr VEC_store_via_HL = $50
!addr VEC_fetch_via_IX_d = $52
!addr VEC_fetch_via_IY_d = $54
!addr VEC_store_via_IX_d = $56
!addr VEC_store_via_IY_d = $58
!addr VEC_fetch_via_nn = $5A
!addr VEC_store_via_nn = $5C
!addr VEC_fetch_via_plus1 = $5E
!addr VEC_store_via_plus1 = $60 ; XXX jump to next directly?
!addr VEC_xchng_stack_lo = $62
!addr VEC_xchng_stack_hi = $64
;
; Constant/macros definitions
@@ -150,5 +149,4 @@
; Helper tables for CPU emulation, downwards from $2000
;
!addr z80_atable_mi_bank0 = $1FF0 ; table for bank 0 memory address conversion
!addr z80_atable_hi_bank0 = $1FE0 ; table for bank 0 memory address conversion
!addr z80_atable_bank0 = $1FE0 ; table for bank 0 memory address conversion
src/zvm_m65/Z80_instr_shftrot_RL.s
+2 -2
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@@ -18,7 +18,7 @@
!macro Z80_RL_VIA_HL {
jsr (VEC_fetch_via_HL_back)
jsr (VEC_fetch_via_HL)
clc
bbr0 REG_F, @1
@@ -26,7 +26,7 @@
@1:
rol
sta [PTR_DATA],z
sta [REG_HL],z
bra Z80_common_RL_VIA
}
src/zvm_m65/Z80_instr_shftrot_RLC.s
+2 -2
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@@ -18,7 +18,7 @@
!macro Z80_RLC_VIA_HL {
jsr (VEC_fetch_via_HL_back)
jsr (VEC_fetch_via_HL)
tax
rol
@@ -26,7 +26,7 @@
rol
sta [PTR_DATA],z
sta [REG_HL],z
bra Z80_common_RLC_VIA
}
src/zvm_m65/Z80_instr_shftrot_RR.s
+2 -2
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@@ -18,7 +18,7 @@
!macro Z80_RR_VIA_HL {
jsr (VEC_fetch_via_HL_back)
jsr (VEC_fetch_via_HL)
clc
bbr0 REG_F, @1
@@ -26,7 +26,7 @@
@1:
ror
sta [PTR_DATA],z
sta [REG_HL],z
bra Z80_common_RR_VIA
}
src/zvm_m65/Z80_instr_shftrot_RRC.s
+2 -2
View File
@@ -18,7 +18,7 @@
!macro Z80_RRC_VIA_HL {
jsr (VEC_fetch_via_HL_back)
jsr (VEC_fetch_via_HL)
tax
ror
@@ -26,7 +26,7 @@
ror
sta [PTR_DATA],z
sta [REG_HL],z
bra Z80_common_RRC_VIA
}
src/zvm_m65/Z80_instr_shftrot_SLA.s
+2 -2
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@@ -14,10 +14,10 @@
!macro Z80_SLA_VIA_HL {
jsr (VEC_fetch_via_HL_back)
jsr (VEC_fetch_via_HL)
asl
sta [PTR_DATA],z
sta [REG_HL],z
bra Z80_common_SLA_VIA
}
src/zvm_m65/Z80_instr_shftrot_SLL.s
+2 -2
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@@ -15,11 +15,11 @@
!macro Z80_SLL_VIA_HL {
jsr (VEC_fetch_via_HL_back)
jsr (VEC_fetch_via_HL)
sec
rol
sta [PTR_DATA],z
sta [REG_HL],z
bra Z80_common_SLL_VIA
}
src/zvm_m65/Z80_instr_shftrot_SRA.s
+2 -2
View File
@@ -18,7 +18,7 @@
!macro Z80_SRA_VIA_HL {
jsr (VEC_fetch_via_HL_back)
jsr (VEC_fetch_via_HL)
tax
ror
@@ -26,7 +26,7 @@
ror
sta [PTR_DATA],z
sta [REG_HL],z
bra Z80_common_SRA_VIA
}
src/zvm_m65/Z80_instr_shftrot_SRL.s
+2 -2
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@@ -15,11 +15,11 @@
!macro Z80_SRL_VIA_HL {
jsr (VEC_fetch_via_HL_back)
jsr (VEC_fetch_via_HL)
clc
ror
sta [PTR_DATA],z
sta [REG_HL],z
bra Z80_common_SRL_VIA
}
src/zvm_m65/z80_instr_bit.s
+32 -32
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@@ -872,51 +872,51 @@ Z80_instr_CB_FF: ; SET 7,A
Z80_instr_CB_C6: ; SET 0,(HL)
jsr (VEC_fetch_via_HL_back)
jsr (VEC_fetch_via_HL)
ora #%00000001
jmp ZVM_store_next
jmp ZVM_store_via_HL_next
Z80_instr_CB_CE: ; SET 1,(HL)
jsr (VEC_fetch_via_HL_back)
jsr (VEC_fetch_via_HL)
ora #%00000010
jmp ZVM_store_next
jmp ZVM_store_via_HL_next
Z80_instr_CB_D6: ; SET 2,(HL)
jsr (VEC_fetch_via_HL_back)
jsr (VEC_fetch_via_HL)
ora #%00000100
jmp ZVM_store_next
jmp ZVM_store_via_HL_next
Z80_instr_CB_DE: ; SET 3,(HL)
jsr (VEC_fetch_via_HL_back)
jsr (VEC_fetch_via_HL)
ora #%00001000
jmp ZVM_store_next
jmp ZVM_store_via_HL_next
Z80_instr_CB_E6: ; SET 4,(HL)
jsr (VEC_fetch_via_HL_back)
jsr (VEC_fetch_via_HL)
ora #%00010000
jmp ZVM_store_next
jmp ZVM_store_via_HL_next
Z80_instr_CB_EE: ; SET 5,(HL)
jsr (VEC_fetch_via_HL_back)
jsr (VEC_fetch_via_HL)
ora #%00100000
jmp ZVM_store_next
jmp ZVM_store_via_HL_next
Z80_instr_CB_F6: ; SET 6,(HL)
jsr (VEC_fetch_via_HL_back)
jsr (VEC_fetch_via_HL)
ora #%01000000
jmp ZVM_store_next
jmp ZVM_store_via_HL_next
Z80_instr_CB_FE: ; SET 7,(HL)
jsr (VEC_fetch_via_HL_back)
jsr (VEC_fetch_via_HL)
ora #%10000000
jmp ZVM_store_next
jmp ZVM_store_via_HL_next
Z80_instr_xDCB_C6: ; SET 0,(IXY+d)
@@ -1256,51 +1256,51 @@ Z80_instr_CB_BF: ; RES 7,A
Z80_instr_CB_86: ; RES 0,(HL)
jsr (VEC_fetch_via_HL_back)
jsr (VEC_fetch_via_HL)
and #%11111110
jmp ZVM_store_next
jmp ZVM_store_via_HL_next
Z80_instr_CB_8E: ; RES 1,(HL)
jsr (VEC_fetch_via_HL_back)
jsr (VEC_fetch_via_HL)
and #%11111101
jmp ZVM_store_next
jmp ZVM_store_via_HL_next
Z80_instr_CB_96: ; RES 2,(HL)
jsr (VEC_fetch_via_HL_back)
jsr (VEC_fetch_via_HL)
and #%11111011
jmp ZVM_store_next
jmp ZVM_store_via_HL_next
Z80_instr_CB_9E: ; RES 3,(HL)
jsr (VEC_fetch_via_HL_back)
jsr (VEC_fetch_via_HL)
and #%11110111
jmp ZVM_store_next
jmp ZVM_store_via_HL_next
Z80_instr_CB_A6: ; RES 4,(HL)
jsr (VEC_fetch_via_HL_back)
jsr (VEC_fetch_via_HL)
and #%11101111
jmp ZVM_store_next
jmp ZVM_store_via_HL_next
Z80_instr_CB_AE: ; RES 5,(HL)
jsr (VEC_fetch_via_HL_back)
jsr (VEC_fetch_via_HL)
and #%11011111
jmp ZVM_store_next
jmp ZVM_store_via_HL_next
Z80_instr_CB_B6: ; RES 6,(HL)
jsr (VEC_fetch_via_HL_back)
jsr (VEC_fetch_via_HL)
and #%10111111
jmp ZVM_store_next
jmp ZVM_store_via_HL_next
Z80_instr_CB_BE: ; RES 7,(HL)
jsr (VEC_fetch_via_HL_back)
jsr (VEC_fetch_via_HL)
and #%01111111
jmp ZVM_store_next
jmp ZVM_store_via_HL_next
Z80_instr_xDCB_86: ; RES 0,(IXY+d)
src/zvm_m65/z80_instr_math_8bit.s
+4 -4
View File
@@ -612,10 +612,10 @@ Z80_common_INC:
Z80_instr_34: ; INC (HL)
jsr (VEC_fetch_via_HL_back)
jsr (VEC_fetch_via_HL)
tax
inc
sta [PTR_DATA],z
sta [REG_HL],z
bra Z80_common_INC
Z80_instr_DD_34: ; INC (IX+d)
@@ -668,10 +668,10 @@ Z80_common_DEC:
Z80_instr_35: ; DEC (HL)
jsr (VEC_fetch_via_HL_back)
jsr (VEC_fetch_via_HL)
tax
dec
sta [PTR_DATA],z
sta [REG_HL],z
bra Z80_common_DEC
Z80_instr_DD_35: ; DEC (IX+d)
src/zvm_m65/z80_instr_rotate_shift.s
+4 -4
View File
@@ -8,7 +8,7 @@
Z80_instr_ED_67: ; RRD
jsr (VEC_fetch_via_HL_back)
jsr (VEC_fetch_via_HL)
sta REG_TMP1
lda REG_A
@@ -43,11 +43,11 @@ Z80_instr_ED_67: ; RRD
sta REG_F
lda REG_TMP1
jmp ZVM_store_next
jmp ZVM_store_via_HL_next
Z80_instr_ED_6F: ; RLD
jsr (VEC_fetch_via_HL_back)
jsr (VEC_fetch_via_HL)
sta REG_TMP1
lda REG_A
@@ -81,7 +81,7 @@ Z80_instr_ED_6F: ; RLD
sta REG_F
lda REG_TMP1
jmp ZVM_store_next
jmp ZVM_store_via_HL_next
Z80_instr_07: ; RLCA
src/zvm_m65/z80_reset.s
+5 -15
View File
@@ -25,24 +25,14 @@ Z80_reset:
; The engine requires all the Z80 visible memory to be present within the 1st 16MB,
; so set the most significant bytes of 32-bit pointers to 0.
stz REG_BC_EXT1+1
stz REG_DE_EXT1+1
stz REG_HL_EXT1+1
stz REG_SP_EXT1+1
stz REG_PC_EXT1+1
stz REG_BC_EXT+1
stz REG_DE_EXT+1
stz REG_HL_EXT+1
stz REG_SP_EXT+1
stz REG_PC_EXT+1
stz PTR_IXY_d+3
stz PTR_DATA+3
; Some pointers are useful for bank 0 only - we can set another byte there
lda #$05
sta REG_BC_EXT1+0
sta REG_DE_EXT1+0
sta REG_HL_EXT1+0
sta REG_SP_EXT1+0
sta REG_PC_EXT1+0
; Default bank is 1 (the fastest, continuous memory)
jmp ZVM_set_bank_1
src/zvm_m65/z80_table_gen.s
+8 -38
View File
@@ -10,53 +10,23 @@ z80_table_gen:
!byte 0
;
; Generating: z80_atable_mi_bank0, z80_atable_hi_bank0
; Generating: z80_atable_bank0
; Dependencies: NONE
; Destroys: NONE
;
ldx #$00
@loop_atable_bank0:
cpx #$C0
bcs @addr_common
; Memory area $0000-$BFFF - maps somewhere to $0xxxx range - 48KB total
lda #$00
sta z80_atable_hi_bank0, x
lda #$04 ; $0000-$DFFF maps to $40000-$4DFFF (bank 0 RAM)
cpx #$E0
bcc @loop_atable_bank0_gotit
inc ; $E000-$FFFF maps to $5E000-$5FFFF (common RAM)
txa
cmp #$60
bcc @addr_lo
@loop_atable_bank0_gotit:
@addr_hi:
; Memory area $6000-$BFFF - maps to $0C000 - $0FFFF - 24 KB
clc
adc #$40
@addr_lo:
; Memory area $0000-$5FFF - maps to $02000 - $07FFF - 24 KB
adc #$20
sta z80_atable_mi_bank0, x
bra @loop_atable_next
@addr_common:
; Memory area $C000-$FFFF - maps to $5C000-$5FFFF - 16KB
lda #$05
sta z80_atable_hi_bank0, x
txa
sta z80_atable_mi_bank0, x
@loop_atable_next:
sta z80_atable_bank0, x
inx
bne @loop_atable_bank0
src/zvm_m65/zvm_banking.s
+16 -28
View File
@@ -41,10 +41,16 @@ ZVM_set_bank_1:
; XXX use DMAgic to switch banks (vectors on zeropage)
; Since all the Z80 bank 1 memory is located in $0005:$xxxx,
; we can set some bytes in certain pointers for faster execution
; we can set bytes in certain pointers for faster execution
lda #$05
sta REG_BC_EXT
sta REG_DE_EXT
sta REG_HL_EXT
sta REG_SP_EXT
sta REG_PC_EXT
sta PTR_IXY_d+2
sta PTR_DATA+2
@@ -56,19 +62,12 @@ ZVM_set_bank_1:
ZVM_bank0_fetch_via_PC_inc:
lda REG_PC+0
sta PTR_DATA+0
ldy REG_PC+1
lda z80_atable_mi_bank0,y
sta PTR_DATA+1
lda z80_atable_hi_bank0,y
sta PTR_DATA+2
lda z80_atable_bank0,y
sta REG_PC_EXT+0
; FALLTROUGH
lda [PTR_DATA], z
inw REG_PC
rts
ZVM_bank1_fetch_via_PC_inc:
lda [REG_PC], z
@@ -78,18 +77,11 @@ ZVM_bank1_fetch_via_PC_inc:
ZVM_bank0_fetch_stack:
ldx REG_SP+0
stx PTR_DATA+0
ldy REG_SP+1
ldx z80_atable_mi_bank0,y
stx PTR_DATA+1
ldx z80_atable_hi_bank0,y
stx PTR_DATA+2
lda z80_atable_bank0,y
sta REG_PC_EXT
lda [PTR_DATA], z
inw REG_SP
rts
; FALLTROUGH
ZVM_bank1_fetch_stack:
@@ -102,13 +94,9 @@ ZVM_bank0_store_stack:
dew REG_SP
ldx REG_SP+0
stx PTR_DATA+0
ldy REG_SP+1
ldx z80_atable_mi_bank0,y
stx PTR_DATA+1
ldx z80_atable_hi_bank0,y
stx PTR_DATA+2
ldx z80_atable_bank0,y
stx REG_SP_EXT
sta [PTR_DATA], z
src/zvm_m65/zvm_core.s
+2 -2
View File
@@ -70,9 +70,9 @@ ZVM_entry:
jmp zvm_BIOS_00_BOOT
ZVM_store_next:
ZVM_store_via_HL_next:
sta [PTR_DATA],z
sta [REG_HL],z
; FALLTROUGH