119 lines
3.0 KiB
ArmAsm
119 lines
3.0 KiB
ArmAsm
;; Receive a byte from the IEC bus.
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;; reference http://www.zimmers.net/anonftp/pub/cbm/programming/serial-bus.pdf
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;; page 11.
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;; XXX rework this, according to pagetable.com
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iec_rx_byte:
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rts
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; ;; First, we wait for the talker to release the CLK line.
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; ;; XXX jsr iec_wait_for_clock_release
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; ;; We then release the data line
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; ;; (We can use this routine, since we weren't holding CLK, anyway)
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; jsr iec_release_clk_and_data
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; ;; Wait for talker to assert CLK.
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; ;; If >200usec, then it is EOI and we have to assert the
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; ;; DATA line for 60 usec to tell the TALKER that we have
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; ;; acknowledged the EOI.
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; ldx #20
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iec_rx_clk_wait:
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; ;; Loop takes 11 usec, so ~20 iterations for 200usec timeout
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; lda $dd00
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; rol
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; bpl not_eoi
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; dex
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; cpx #$21
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; bne not_rx_timeout
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; ;; Time out waiting for CLK to assert again.
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; ;; = error
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; sec
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; rts
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not_rx_timeout:
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; cpx #$00
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; bpl iec_rx_clk_wait
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; ;; Remember EOI condition
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; lda IOSTATUS
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; ora #$40
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; sta IOSTATUS
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; ;; EOI timeout: So pulse DATA line for 60 usec
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; jsr iec_assert_data
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; jsr iec_wait60us
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; jsr iec_release_clk_and_data
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; ;; And still wait for CLK to be asserted
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; ;; XXX - This will cause periodic EOI pulses if the sender takes too long.
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; ;; That is probably ok.
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; ldx #$7f
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; jmp iec_rx_clk_wait
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not_eoi:
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; ;; CLK is now low. Latch input bits in on rising edge
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; ;; of CLK, eight times for eight bits.
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; ldx #7
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; ;; Get empty byte to load into.
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; lda #$00
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; pha
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iec_rx_bit_loop:
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; ;; Wait for CLK to release
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; ;; jsr iec_wait_for_clock_release
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; ;; (we do this implicitly below, with a tighter routine,
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; ;; so that we don't have timing problems, as the requirements
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; ;; are quite tight. Basically we need to read the clock and data
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; ;; bit from the same byte read.
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; ;; DATA now has the next bit, but inverted (well, except that it turns out not to be).
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; ;; DATA is in bit7, which is a bit annoying.
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; ;; But we can clock it out with a ROL instruction
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; ;; so that it is in C. We can then ROR it into the
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; ;; partial data byte.
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; ;; We use ROR so that we shift in from the top, so that
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; ;; the first bit we shift in ends up in bit 0 after all
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; ;; 8 bits have been read.
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; ;; ODD: For some reason we don't need to invert the
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; ;; received bits. This is weird, because we invert them
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; ;; on the way out, and everything in the protocol seems
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; ;; to indicate that we sould do so. But experimentation
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; ;; has confirmed the bits don't need inversion on reception.
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; ;; Move data bit into C flag, and loop until bit 6 clears
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; ;; i.e., the clock has been released.
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;* LDA $DD00
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; ROL
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; bpl -
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; ;; Pull it into the data byte
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;; pla
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; ROR
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; pha
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; ;; Wait for CLK to re-assert
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; jsr iec_wait_for_clock_assert
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; ;; More bits?
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; dex
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; bpl iec_rx_bit_loop
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; ;; Then we must within 1000usec acknowledge the frame by
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; ;; asserting DATA. At this point, CLK is asserted by the
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; ;; talker and DATA by us, i.e., we are ready to receive
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; ;; the next byte. (p11).
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; jsr iec_assert_data
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; ;; Retreive the received byte
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; PLA
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; ;; Return no-error
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; CLC
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; RTS
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