176 lines
4.0 KiB
ArmAsm
176 lines
4.0 KiB
ArmAsm
;; #LAYOUT# STD * #TAKE
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;; #LAYOUT# * KERNAL_0 #TAKE
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;; #LAYOUT# * * #IGNORE
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; Receive a byte from the IEC bus.
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; Implemented based on https://www.pagetable.com/?p=1135, https://github.com/mist64/cbmbus_doc,
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; http://www.zimmers.net/anonftp/pub/cbm/programming/serial-bus.pdf (page 11)
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;
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; Preserves .X and .Y registers
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!ifdef CONFIG_IEC {
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!ifdef CONFIG_IEC_JIFFYDOS {
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iec_rx_dispatch:
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!ifdef CONFIG_MB_M65 {
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; If in native mode, switch to 1 MHz
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jsr m65_iec_slow
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}
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lda IECPROTO
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cmp #IEC_JIFFY
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+beq jiffydos_rx_byte
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; FALLTROUGH
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} ; CONFIG_IEC_JIFFYDOS
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iec_rx_byte:
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!ifdef CONFIG_MB_M65 { !ifndef CONFIG_IEC_JIFFYDOS {
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; If in native mode, switch to 1 MHz
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jsr m65_iec_slow
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} }
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; Store .X and .Y on the stack - preserve them
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+phx_trash_a
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+phy_trash_a
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; Timing is critical here - execute on disabled IRQs
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; The best practice would be to do PHP first, but it seems this is not
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; what the original ROM does; furthermore, pushing additional bytes to
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; stack can wreck autostart softwaree loading at $0100
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sei
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; First, we wait for the talker to release the CLK line
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jsr iec_wait_for_clk_release
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; We then release the DATA to signal we are ready
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; We can use this routine, since we were not pulling CLK anyway
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jsr iec_release_clk_data
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; Wait till data line is released (someone else might be holding it)
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jsr iec_wait_for_data_release
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; Check if EOI
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jsr iec_rx_check_eoi
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!ifdef CONFIG_IEC_DOLPHINDOS {
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; Check if DolphinDOS was detected
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lda IECPROTO
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cmp #IEC_DOLPHIN
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bne iec_rx_no_dolphindos
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; For DolphinDOS just fetch the byte from parallel port
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lda CIA2_PRB
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pha
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+bra iec_rx_acknowledge
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iec_rx_no_dolphindos:
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} ; CONFIG_IEC_DOLPHINDOS
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; Latch input bits in on rising edge of CLK, eight times for eight bits.
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ldx #7
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; Get empty byte to load into.
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lda #$00
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pha
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iec_rx_bit_loop:
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; Wait for CLK to release
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jsr iec_wait_for_clk_release
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; (we do this implicitly below, with a tighter routine,
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; so that we do not have timing problems, as the requirements
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; are quite tight. Basically we need to read the clock and data
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; bit from the same byte read.
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; DATA now has the next bit, but inverted (well, except that it turns out not to be).
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; DATA is in bit 7, which is a bit annoying.
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; But we can clock it out with a ROL instruction
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; so that it is in C. We can then ROR it into the
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; partial data byte.
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; We use ROR so that we shift in from the top, so that
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; the first bit we shift in ends up in bit 0 after all
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; 8 bits have been read.
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; ODD: For some reason we don't need to invert the
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; received bits. This is weird, because we invert them
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; on the way out, and everything in the protocol seems
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; to indicate that we sould do so. But experimentation
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; has confirmed the bits don't need inversion on reception.
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; Move data bit into C flag, and loop until bit 6 clears
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; i.e., the clock has been released.
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@1:
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lda CIA2_PRA
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rol
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bpl @1
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; Pull it into the data byte
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pla
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ror
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pha
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; Wait for CLK to be pulled again, over 300 usec (307 cycles on NTSC)
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; consider this a timeout
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ldy #$19 ; 2 cycles
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iec_rx_clk_wait2:
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lda CIA2_PRA ; 4 cycles
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rol ; 2 cycles, to put CLK in as the last bit
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bpl @2 ; 2 cycles if not jumped
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dey ; 2 cycles
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bne iec_rx_clk_wait2 ; 3 cycles if jumped
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; Timeout
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jsr kernalstatus_EOI
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pla
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+bra iec_rx_end
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@2:
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; More bits?
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dex
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bpl iec_rx_bit_loop
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; FALLTROUGH
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iec_rx_acknowledge:
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; Then we must within 1000 usec acknowledge the byte by
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; pulling DATA. At this point, CLK is pulled by the
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; talker and DATA by us, i.e., we are ready to receive
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; the next byte. (p11).
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jsr iec_release_clk_pull_data
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; Retrieve the received byte
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pla
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; Restore registers
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sta TBTCNT ; $A4 is a byte buffer according to http://sta.c64.org/cbm64mem.html
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; FALLTROUGH
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iec_rx_end:
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!ifdef CONFIG_MB_M65 {
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; If in native mode, switch back to fast mode
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jsr m65_iec_fast
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}
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+ply_trash_a
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+plx_trash_a
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lda TBTCNT
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clc
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cli
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rts
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}
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