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some cleanup, mainly Z80 related

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FeralChild64 committed 2021-01-02 19:52:02 +01:00
1 parent dc4edbb81c
commit 690b2b832d
22 files changed
+190 -270
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src/basic/wedge/wedge_dos.s
+1 -1
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@@ -34,7 +34,7 @@ wedge_dos:
; Close all the channels, so that wedge has full control
jsr JCLALL
; Set file parameters, channel 15 is a typical one for commands
; Set file parameters, channel 15 is a typical one for commands
jsr SELDEV ; sets .X register
lda #$0F
ldy #$0F
src/zvm_m65/,aliases_zvm.s
+67 -33
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@@ -77,37 +77,6 @@
; $3E ; 2 bytes - reserved
;
; Memory banking vectors - every single routine destroys .Y in case of bank 0
;
; XXX inline some of these routines - provide separate opcode implementations for various banks
!addr zvm_bankvectors__start = $40
!addr VEC_fetch_via_PC_inc = $40 ; fetch to .A from (PC), increment PC afterwards
!addr VEC_fetch_stack = $42 ; fetch to .A - stack POP operation
!addr VEC_store_stack = $44 ; store .A - stack PUSH operation, destroys .X
; XXX implement routines for vectors below
!addr VEC_fetch_via_BC = $46
!addr VEC_store_via_BC = $48
!addr VEC_fetch_via_DE = $4A
!addr VEC_store_via_DE = $4C
!addr VEC_fetch_via_HL = $4E
!addr VEC_store_via_HL = $50
!addr VEC_fetch_via_IX_d = $52
!addr VEC_fetch_via_IY_d = $54
!addr VEC_store_via_IX_d = $56
!addr VEC_store_via_IY_d = $58
!addr VEC_fetch_via_nn = $5A
!addr VEC_store_via_nn = $5C
!addr VEC_fetch_via_plus1 = $5E
!addr VEC_store_via_plus1 = $60 ; XXX jump to next directly?
!addr VEC_xchng_stack_lo = $62
!addr VEC_xchng_stack_hi = $64
;
; Constant/macros definitions
;
@@ -145,8 +114,73 @@
!macro Z80_PUT_1_CF { smb0 REG_F }
!macro Z80_PUT_0_CF { rmb0 REG_F }
;
; Helper tables for CPU emulation, downwards from $2000
; Macros to abstract memory access
;
!addr z80_atable_bank0 = $1FE0 ; table for bank 0 memory address conversion
!macro Z80_FETCH_VIA_PC_INC { ; fetch to .A from (PC), increment PC afterwards
lda [REG_PC], z
inw REG_PC
}
!macro Z80_FETCH_STACK { ; fetch to .A - stack POP operation
lda [REG_SP], z
inw REG_SP
}
!macro Z80_STORE_STACK { ; store .A - stack PUSH operation
dew REG_SP
sta [REG_SP], z
}
!macro Z80_FETCH_VIA_BC { ; fetch to .A from (BC)
lda [REG_BC], z
}
!macro Z80_STORE_VIA_BC { ; store .A to (BC)
sta [REG_BC], z
}
!macro Z80_FETCH_VIA_DE { ; fetch to .A from (DE)
lda [REG_DE], z
}
!macro Z80_STORE_VIA_DE { ; store .A to (DE)
sta [REG_DE], z
}
!macro Z80_FETCH_VIA_HL { ; fetch to .A from (HL)
lda [REG_HL], z
}
!macro Z80_STORE_VIA_HL { ; store .A to (HL)
sta [REG_HL], z
}
!macro Z80_STORE_BACK_VIA_HL { ; store .A to (HL) when instruction already used Z80_FETCH_VIA_HL
sta [REG_HL], z
}
; XXX turn vectors below into macros
!addr VEC_fetch_via_IX_d = $52
!addr VEC_fetch_via_IY_d = $54
!addr VEC_store_via_IX_d = $56
!addr VEC_store_via_IY_d = $58
!addr VEC_fetch_via_nn = $5A
!addr VEC_store_via_nn = $5C
!addr VEC_fetch_via_plus1 = $5E
!addr VEC_store_via_plus1 = $60 ; XXX jump to next directly?
!addr VEC_xchng_stack_lo = $62
!addr VEC_xchng_stack_hi = $64
src/zvm_m65/Z80_instr_shftrot_RL.s
+2 -2
View File
@@ -18,7 +18,7 @@
!macro Z80_RL_VIA_HL {
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
clc
bbr0 REG_F, @1
@@ -26,7 +26,7 @@
@1:
rol
sta [REG_HL],z
+Z80_STORE_BACK_VIA_HL
bra Z80_common_RL_VIA
}
src/zvm_m65/Z80_instr_shftrot_RLC.s
+2 -2
View File
@@ -18,7 +18,7 @@
!macro Z80_RLC_VIA_HL {
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
tax
rol
@@ -26,7 +26,7 @@
rol
sta [REG_HL],z
+Z80_STORE_BACK_VIA_HL
bra Z80_common_RLC_VIA
}
src/zvm_m65/Z80_instr_shftrot_RR.s
+2 -2
View File
@@ -18,7 +18,7 @@
!macro Z80_RR_VIA_HL {
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
clc
bbr0 REG_F, @1
@@ -26,7 +26,7 @@
@1:
ror
sta [REG_HL],z
+Z80_STORE_BACK_VIA_HL
bra Z80_common_RR_VIA
}
src/zvm_m65/Z80_instr_shftrot_RRC.s
+2 -2
View File
@@ -18,7 +18,7 @@
!macro Z80_RRC_VIA_HL {
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
tax
ror
@@ -26,7 +26,7 @@
ror
sta [REG_HL],z
+Z80_STORE_BACK_VIA_HL
bra Z80_common_RRC_VIA
}
src/zvm_m65/Z80_instr_shftrot_SLA.s
+2 -2
View File
@@ -14,10 +14,10 @@
!macro Z80_SLA_VIA_HL {
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
asl
sta [REG_HL],z
+Z80_STORE_BACK_VIA_HL
bra Z80_common_SLA_VIA
}
src/zvm_m65/Z80_instr_shftrot_SLL.s
+2 -2
View File
@@ -15,11 +15,11 @@
!macro Z80_SLL_VIA_HL {
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
sec
rol
sta [REG_HL],z
+Z80_STORE_BACK_VIA_HL
bra Z80_common_SLL_VIA
}
src/zvm_m65/Z80_instr_shftrot_SRA.s
+2 -2
View File
@@ -18,7 +18,7 @@
!macro Z80_SRA_VIA_HL {
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
tax
ror
@@ -26,7 +26,7 @@
ror
sta [REG_HL],z
+Z80_STORE_BACK_VIA_HL
bra Z80_common_SRA_VIA
}
src/zvm_m65/Z80_instr_shftrot_SRL.s
+2 -2
View File
@@ -15,11 +15,11 @@
!macro Z80_SRL_VIA_HL {
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
clc
ror
sta [REG_HL],z
+Z80_STORE_BACK_VIA_HL
bra Z80_common_SRL_VIA
}
src/zvm_m65/z80_instr_bit.s
+24 -24
View File
@@ -360,56 +360,56 @@ Z80_common_bit7_1:
Z80_instr_CB_46: ; BIT 0,(HL)
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
and #%00000001
bne Z80_common_bitHL_1
bra Z80_common_bitHL_0
Z80_instr_CB_4E: ; BIT 1,(HL)
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
and #%00000010
bne Z80_common_bitHL_1
bra Z80_common_bitHL_0
Z80_instr_CB_56: ; BIT 2,(HL)
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
and #%00000100
bne Z80_common_bitHL_1
bra Z80_common_bitHL_0
Z80_instr_CB_5E: ; BIT 3,(HL)
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
and #%00001000
bne Z80_common_bitHL_1
bra Z80_common_bitHL_0
Z80_instr_CB_66: ; BIT 4,(HL)
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
and #%00010000
bne Z80_common_bitHL_1
bra Z80_common_bitHL_0
Z80_instr_CB_6E: ; BIT 5,(HL)
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
and #%00100000
bne Z80_common_bitHL_1
bra Z80_common_bitHL_0
Z80_instr_CB_76: ; BIT 6,(HL)
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
and #%01000000
bne Z80_common_bitHL_1
bra Z80_common_bitHL_0
Z80_instr_CB_7E: ; BIT 7,(HL)
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
and #%10000000
beq Z80_common_bitHL_0
@@ -872,49 +872,49 @@ Z80_instr_CB_FF: ; SET 7,A
Z80_instr_CB_C6: ; SET 0,(HL)
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
ora #%00000001
jmp ZVM_store_via_HL_next
Z80_instr_CB_CE: ; SET 1,(HL)
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
ora #%00000010
jmp ZVM_store_via_HL_next
Z80_instr_CB_D6: ; SET 2,(HL)
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
ora #%00000100
jmp ZVM_store_via_HL_next
Z80_instr_CB_DE: ; SET 3,(HL)
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
ora #%00001000
jmp ZVM_store_via_HL_next
Z80_instr_CB_E6: ; SET 4,(HL)
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
ora #%00010000
jmp ZVM_store_via_HL_next
Z80_instr_CB_EE: ; SET 5,(HL)
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
ora #%00100000
jmp ZVM_store_via_HL_next
Z80_instr_CB_F6: ; SET 6,(HL)
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
ora #%01000000
jmp ZVM_store_via_HL_next
Z80_instr_CB_FE: ; SET 7,(HL)
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
ora #%10000000
jmp ZVM_store_via_HL_next
@@ -1256,49 +1256,49 @@ Z80_instr_CB_BF: ; RES 7,A
Z80_instr_CB_86: ; RES 0,(HL)
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
and #%11111110
jmp ZVM_store_via_HL_next
Z80_instr_CB_8E: ; RES 1,(HL)
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
and #%11111101
jmp ZVM_store_via_HL_next
Z80_instr_CB_96: ; RES 2,(HL)
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
and #%11111011
jmp ZVM_store_via_HL_next
Z80_instr_CB_9E: ; RES 3,(HL)
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
and #%11110111
jmp ZVM_store_via_HL_next
Z80_instr_CB_A6: ; RES 4,(HL)
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
and #%11101111
jmp ZVM_store_via_HL_next
Z80_instr_CB_AE: ; RES 5,(HL)
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
and #%11011111
jmp ZVM_store_via_HL_next
Z80_instr_CB_B6: ; RES 6,(HL)
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
and #%10111111
jmp ZVM_store_via_HL_next
Z80_instr_CB_BE: ; RES 7,(HL)
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
and #%01111111
jmp ZVM_store_via_HL_next
src/zvm_m65/z80_instr_block.s
+8 -8
View File
@@ -10,8 +10,8 @@ Z80_instr_ED_A0: ; LDI
and #($FF - Z80_HF - Z80_PF - Z80_NF)
sta REG_F
jsr (VEC_fetch_via_HL)
jsr (VEC_store_via_DE)
+Z80_FETCH_VIA_HL
+Z80_STORE_VIA_DE
inw REG_HL
inw REG_DE
@@ -27,8 +27,8 @@ Z80_instr_ED_B0: ; LDIR
and #($FF - Z80_HF - Z80_PF - Z80_NF)
sta REG_F
@1:
jsr (VEC_fetch_via_HL)
jsr (VEC_store_via_DE)
+Z80_FETCH_VIA_HL
+Z80_STORE_VIA_DE
inw REG_HL
inw REG_DE
@@ -43,8 +43,8 @@ Z80_instr_ED_A8: ; LDD
and #($FF - Z80_HF - Z80_PF - Z80_NF)
sta REG_F
jsr (VEC_fetch_via_HL)
jsr (VEC_store_via_DE)
+Z80_FETCH_VIA_HL
+Z80_STORE_VIA_DE
dew REG_HL
dew REG_DE
@@ -60,8 +60,8 @@ Z80_instr_ED_B8: ; LDDR
and #($FF - Z80_HF - Z80_PF - Z80_NF)
sta REG_F
@1:
jsr (VEC_fetch_via_HL)
jsr (VEC_store_via_DE)
+Z80_FETCH_VIA_HL
+Z80_STORE_VIA_DE
dew REG_HL
dew REG_DE
src/zvm_m65/z80_instr_call_return.s
+12 -12
View File
@@ -6,19 +6,19 @@
Z80_instr_CD: ; CALL nn
jsr (VEC_fetch_via_PC_inc)
pha
jsr (VEC_fetch_via_PC_inc)
pha
+Z80_FETCH_VIA_PC_INC
tax
+Z80_FETCH_VIA_PC_INC
tay
lda REG_PC+1
jsr (VEC_store_stack)
+Z80_STORE_STACK
lda REG_PC+0
jsr (VEC_store_stack)
+Z80_STORE_STACK
pla
tya
sta REG_PC+1
pla
txa
sta REG_PC+0
jmp ZVM_next
@@ -92,9 +92,9 @@ Z80_illeg_ED_7D: ; RETN
Z80_instr_ED_4D: ; RETTI
Z80_instr_C9: ; RET
jsr (VEC_fetch_stack)
+Z80_FETCH_STACK
sta REG_PC+0
jsr (VEC_fetch_stack)
+Z80_FETCH_STACK
sta REG_PC+1
jmp ZVM_next
@@ -142,9 +142,9 @@ Z80_instr_F8: ; RET M
!macro Z80_RST .P {
lda REG_PC+1
jsr (VEC_store_stack)
+Z80_STORE_STACK
lda REG_PC+0
jsr (VEC_store_stack)
+Z80_STORE_STACK
lda #$00
sta REG_PC+1
lda #.P
src/zvm_m65/z80_instr_io.s
+2 -2
View File
@@ -8,7 +8,7 @@
Z80_instr_DB: ; IN A,(n)
jsr (VEC_fetch_via_PC_inc)
+Z80_FETCH_VIA_PC_INC
sta ADDR_IO+0
lda REG_A
sta ADDR_IO+1
@@ -56,7 +56,7 @@ Z80_illeg_ED_70: +Z80_IN_NULL ;
Z80_instr_D3: ; OUT (n),A
jsr (VEC_fetch_via_PC_inc)
+Z80_FETCH_VIA_PC_INC
sta ADDR_IO+0
lda REG_A
sta ADDR_IO+1
src/zvm_m65/z80_instr_jump.s
+3 -3
View File
@@ -6,9 +6,9 @@
Z80_instr_C3: ; JP nn
jsr (VEC_fetch_via_PC_inc)
+Z80_FETCH_VIA_PC_INC
sta REG_PC+0
jsr (VEC_fetch_via_PC_inc)
+Z80_FETCH_VIA_PC_INC
sta REG_PC+1
jmp ZVM_next
@@ -102,7 +102,7 @@ Z80_instr_18: ; JR e
@1:
rmb7 REG_PC+0
@2:
jsr (VEC_fetch_via_PC_inc)
+Z80_FETCH_VIA_PC_INC
tax
lda z80_otable_displacement,x
clc
src/zvm_m65/z80_instr_load_16bit.s
+6 -6
View File
@@ -5,9 +5,9 @@
!macro Z80_LD_REGnn_nn .REGnn {
jsr (VEC_fetch_via_PC_inc)
+Z80_FETCH_VIA_PC_INC
sta .REGnn+0
jsr (VEC_fetch_via_PC_inc)
+Z80_FETCH_VIA_PC_INC
sta .REGnn+1
jmp ZVM_next
}
@@ -65,9 +65,9 @@ Z80_instr_ED_7B: +Z80_LD_REGnn_VIA_nn REG_SP ;
!macro Z80_PUSH_REGnn .REGnn {
lda .REGnn+1
jsr (VEC_store_stack)
+Z80_STORE_STACK
lda .REGnn+0
jsr (VEC_store_stack)
+Z80_STORE_STACK
jmp ZVM_next
}
@@ -79,9 +79,9 @@ Z80_instr_DD_E5: +Z80_PUSH_REGnn REG_IX ;
Z80_instr_FD_E5: +Z80_PUSH_REGnn REG_IY ; PUSH IY
!macro Z80_POP_REGnn .REGnn {
jsr (VEC_fetch_stack)
+Z80_FETCH_STACK
sta .REGnn+0
jsr (VEC_fetch_stack)
+Z80_FETCH_STACK
lda .REGnn+1
jmp ZVM_next
}
src/zvm_m65/z80_instr_load_8bit.s
+9 -9
View File
@@ -110,7 +110,7 @@ Z80_illeg_FD_6C: +Z80_LD_REGn_REGn REG_IYL, REG_IYH ;
Z80_illeg_FD_6F: +Z80_LD_REGn_REGn REG_IYL, REG_A ; LD IYL,A
!macro Z80_LD_REGn_n .REGn {
jsr (VEC_fetch_via_PC_inc)
+Z80_FETCH_VIA_PC_INC
sta .REGn
jmp ZVM_next
}
@@ -129,7 +129,7 @@ Z80_illeg_FD_26: +Z80_LD_REGn_n REG_IYH ;
Z80_illeg_FD_2E: +Z80_LD_REGn_n REG_IYL ; LD IYL,n
!macro Z80_LD_REGn_VIA_HL .REGn {
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
sta .REGn
jmp ZVM_next
}
@@ -144,7 +144,7 @@ Z80_instr_7E: +Z80_LD_REGn_VIA_HL REG_A ;
!macro Z80_LD_VIA_HL_REGn .REGn {
lda .REGn
jsr (VEC_store_via_HL)
+Z80_STORE_VIA_HL
jmp ZVM_next
}
@@ -159,24 +159,24 @@ Z80_instr_77: +Z80_LD_VIA_HL_REGn REG_A ;
Z80_instr_02: ; LD (BC),A
lda REG_A
jsr (VEC_store_via_BC)
+Z80_STORE_VIA_BC
jmp ZVM_next
Z80_instr_0A: ; LD A,(BC)
jsr (VEC_fetch_via_BC)
+Z80_FETCH_VIA_BC
sta REG_A
jmp ZVM_next
Z80_instr_12: ; LD (DE),A
lda REG_A
jsr (VEC_store_via_DE)
+Z80_STORE_VIA_DE
jmp ZVM_next
Z80_instr_1A: ; LD A,(DE)
jsr (VEC_fetch_via_DE)
+Z80_FETCH_VIA_DE
sta REG_A
jmp ZVM_next
@@ -250,8 +250,8 @@ Z80_instr_FD_77: +Z80_LD_VIA_IY_d_REG_n REG_A ;
Z80_instr_36: ; LD (HL),n
jsr (VEC_fetch_via_PC_inc)
jsr (VEC_store_via_HL)
+Z80_FETCH_VIA_PC_INC
+Z80_STORE_VIA_HL
jmp ZVM_next
Z80_instr_ED_57: ; LD A,I
src/zvm_m65/z80_instr_math_8bit.s
+20 -20
View File
@@ -8,12 +8,12 @@
!macro Z80_ADD_n {
jsr (VEC_fetch_via_PC_inc)
+Z80_FETCH_VIA_PC_INC
bra Z80_common_add
}
!macro Z80_ADC_n {
jsr (VEC_fetch_via_PC_inc)
+Z80_FETCH_VIA_PC_INC
bbs0 REG_F,Z80_common_adc
jmp Z80_common_add
}
@@ -30,12 +30,12 @@
}
!macro Z80_ADD_VIA_HL {
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
bra Z80_common_add
}
!macro Z80_ADC_VIA_HL {
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
bbs0 REG_F,Z80_common_adc
jmp Z80_common_add
}
@@ -167,12 +167,12 @@ Z80_common_adc:
jmp ZVM_next
!macro Z80_SUB_n {
jsr (VEC_fetch_via_PC_inc)
+Z80_FETCH_VIA_PC_INC
bra Z80_common_sub
}
!macro Z80_SBC_n {
jsr (VEC_fetch_via_PC_inc)
+Z80_FETCH_VIA_PC_INC
bbs0 REG_F,Z80_common_sbc
jmp Z80_common_sub
}
@@ -189,12 +189,12 @@ Z80_common_adc:
}
!macro Z80_SUB_VIA_HL {
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
bra Z80_common_sub
}
!macro Z80_SBC_VIA_HL {
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
bbs0 REG_F,Z80_common_sbc
jmp Z80_common_sub
}
@@ -326,7 +326,7 @@ Z80_common_sbc:
jmp ZVM_next
!macro Z80_CP_n {
jsr (VEC_fetch_via_PC_inc)
+Z80_FETCH_VIA_PC_INC
bra Z80_common_cp
}
@@ -336,7 +336,7 @@ Z80_common_sbc:
}
!macro Z80_CP_VIA_HL {
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
bra Z80_common_cp
}
@@ -426,12 +426,12 @@ Z80_common_cp:
}
!macro Z80_AND_VIA_HL {
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
+Z80_AND_common
}
!macro Z80_AND_n {
jsr (VEC_fetch_via_PC_inc)
+Z80_FETCH_VIA_PC_INC
+Z80_AND_common
}
@@ -486,12 +486,12 @@ Z80_instr_FD_A6: +Z80_AND_VIA_IY_d ;
}
!macro Z80_OR_VIA_HL {
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
+Z80_OR_common
}
!macro Z80_OR_n {
jsr (VEC_fetch_via_PC_inc)
+Z80_FETCH_VIA_PC_INC
+Z80_OR_common
}
@@ -543,12 +543,12 @@ Z80_instr_FD_B6: +Z80_OR_VIA_IY_d ;
}
!macro Z80_XOR_VIA_HL {
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
+Z80_XOR_common
}
!macro Z80_XOR_n {
jsr (VEC_fetch_via_PC_inc)
+Z80_FETCH_VIA_PC_INC
+Z80_XOR_common
}
@@ -612,10 +612,10 @@ Z80_common_INC:
Z80_instr_34: ; INC (HL)
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
tax
inc
sta [REG_HL],z
+Z80_STORE_BACK_VIA_HL
bra Z80_common_INC
Z80_instr_DD_34: ; INC (IX+d)
@@ -668,10 +668,10 @@ Z80_common_DEC:
Z80_instr_35: ; DEC (HL)
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
tax
dec
sta [REG_HL],z
+Z80_STORE_BACK_VIA_HL
bra Z80_common_DEC
Z80_instr_DD_35: ; DEC (IX+d)
src/zvm_m65/z80_instr_rotate_shift.s
+2 -2
View File
@@ -8,7 +8,7 @@
Z80_instr_ED_67: ; RRD
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
sta REG_TMP1
lda REG_A
@@ -47,7 +47,7 @@ Z80_instr_ED_67: ; RRD
Z80_instr_ED_6F: ; RLD
jsr (VEC_fetch_via_HL)
+Z80_FETCH_VIA_HL
sta REG_TMP1
lda REG_A
src/zvm_m65/z80_table_gen.s
+1 -23
View File
@@ -9,35 +9,13 @@ z80_table_gen:
!pet $0D, "Generating CPU tables... "
!byte 0
;
; Generating: z80_atable_bank0
; Dependencies: NONE
; Destroys: NONE
;
ldx #$00
@loop_atable_bank0:
lda #$04 ; $0000-$DFFF maps to $40000-$4DFFF (bank 0 RAM)
cpx #$E0
bcc @loop_atable_bank0_gotit
inc ; $E000-$FFFF maps to $5E000-$5FFFF (common RAM)
@loop_atable_bank0_gotit:
sta z80_atable_bank0, x
inx
bne @loop_atable_bank0
;
; Generating: XXX
; Dependencies: NONE
; Destroys: NONE
;
; XXX add more tables here
; XXX add table generators
;
; The END
src/zvm_m65/zvm_banking.s
+8 -97
View File
@@ -3,23 +3,6 @@
; Z80 Virtual Machine banking support
;
ZVM_bank0_vectab:
!word ZVM_bank0_fetch_via_PC_inc
!word ZVM_bank0_fetch_stack
!word ZVM_bank0_store_stack
; XXX add remaining routines here
ZVM_bank1_vectab:
!word ZVM_bank1_fetch_via_PC_inc
!word ZVM_bank1_fetch_stack
!word ZVM_bank1_store_stack
; XXX add remaining routines here
;
; Bank switching routines
;
@@ -29,22 +12,24 @@ ZVM_set_bank_0:
lda #$00
sta BANK_ID
; XXX use DMAgic to switch banks (vectors on zeropage)
; XXX use DMAgic to copy common memory
rts
lda #$04
bra ZVM_set_bank_common
ZVM_set_bank_1:
lda #$01
sta BANK_ID
; XXX use DMAgic to switch banks (vectors on zeropage)
; Since all the Z80 bank 1 memory is located in $0005:$xxxx,
; we can set bytes in certain pointers for faster execution
; XXX use DMAgic to copy common memory
lda #$05
; FALLTROUGH
ZVM_set_bank_common:
sta REG_BC_EXT
sta REG_DE_EXT
sta REG_HL_EXT
@@ -55,77 +40,3 @@ ZVM_set_bank_1:
sta PTR_DATA+2
rts
;
; Memory access routines
;
ZVM_bank0_fetch_via_PC_inc:
ldy REG_PC+1
lda z80_atable_bank0,y
sta REG_PC_EXT+0
; FALLTROUGH
ZVM_bank1_fetch_via_PC_inc:
lda [REG_PC], z
inw REG_PC
rts
ZVM_bank0_fetch_stack:
ldy REG_SP+1
lda z80_atable_bank0,y
sta REG_PC_EXT
; FALLTROUGH
ZVM_bank1_fetch_stack:
lda [REG_SP], z
inw REG_SP
rts
ZVM_bank0_store_stack:
dew REG_SP
ldy REG_SP+1
ldx z80_atable_bank0,y
stx REG_SP_EXT
sta [PTR_DATA], z
rts
ZVM_bank1_store_stack:
dew REG_SP
sta [REG_SP], z
rts
; XXX cleanup code below
ZVM_fetch_IO:
; XXX fetch addresses via ADDR_IO - but which ones are safe? Should we have a whitelist?
lda #$00
sta REG_A
rts
ZVM_store_IO:
; XXX again, we should have a whitelist of addresses
rts
src/zvm_m65/zvm_core.s
+11 -14
View File
@@ -72,7 +72,7 @@ ZVM_entry:
ZVM_store_via_HL_next:
sta [REG_HL],z
+Z80_STORE_BACK_VIA_HL
; FALLTROUGH
@@ -80,7 +80,7 @@ ZVM_store_via_HL_next:
; Fetch and execute next opcode
jsr (VEC_fetch_via_PC_inc)
+Z80_FETCH_VIA_PC_INC
asl
tax
bcs @1
@@ -155,22 +155,19 @@ Z80_instr_FD: +ZVM_DISPATCH Z80_vectab_FD_0, Z80_vectab_FD_1 ;
; XXX cleanup code below
ZVM_fetch_IO:
; XXX fetch addresses via ADDR_IO - but which ones are safe? Should we have a whitelist?
lda #$00
sta REG_A
rts
ZVM_store_IO:
; XXX again, we should have a whitelist of addresses
rts