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Z80 cleanup

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FeralChild64 authored and FeralChild64 committed 2021-01-26 00:03:07 +01:00
1 parent 2848f2d263
commit a70efc1fa0
15 files changed
+92 -63
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src/zvm_m65/,aliases_zvm.s
+12 -11
View File
@@ -96,17 +96,18 @@
!addr VEC_fetch_via_DE = $4A
!addr VEC_store_via_DE = $4C
!addr VEC_fetch_via_HL = $4E
!addr VEC_store_via_HL = $50
!addr VEC_fetch_via_IX_d = $52
!addr VEC_fetch_via_IY_d = $54
!addr VEC_store_via_IX_d = $56
!addr VEC_store_via_IY_d = $58
!addr VEC_fetch_via_nn = $5A
!addr VEC_store_via_nn = $5C
!addr VEC_fetch_via_plus1 = $5E
!addr VEC_store_via_plus1 = $60 ; XXX jump to next directly?
!addr VEC_xchng_stack_lo = $62
!addr VEC_xchng_stack_hi = $64
!addr VEC_fetch_via_HL_back = $50 ; forces PTR_DATA update
!addr VEC_store_via_HL = $52
!addr VEC_fetch_via_IX_d = $54
!addr VEC_fetch_via_IY_d = $56
!addr VEC_store_via_IX_d = $58
!addr VEC_store_via_IY_d = $5A
!addr VEC_fetch_via_nn = $5C
!addr VEC_store_via_nn = $5E
!addr VEC_fetch_via_plus1 = $60
!addr VEC_store_via_plus1 = $62 ; XXX jump to next directly?
!addr VEC_xchng_stack_lo = $64
!addr VEC_xchng_stack_hi = $68
;
; Constant/macros definitions
src/zvm_m65/Z80_instr_shftrot_RL.s
+1 -1
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@@ -18,7 +18,7 @@
!macro Z80_RL_VIA_HL {
jsr (VEC_fetch_via_HL)
jsr (VEC_fetch_via_HL_back)
clc
bbr0 REG_F, @1
src/zvm_m65/Z80_instr_shftrot_RLC.s
+1 -1
View File
@@ -18,7 +18,7 @@
!macro Z80_RLC_VIA_HL {
jsr (VEC_fetch_via_HL)
jsr (VEC_fetch_via_HL_back)
tax
rol
src/zvm_m65/Z80_instr_shftrot_RR.s
+1 -1
View File
@@ -18,7 +18,7 @@
!macro Z80_RR_VIA_HL {
jsr (VEC_fetch_via_HL)
jsr (VEC_fetch_via_HL_back)
clc
bbr0 REG_F, @1
src/zvm_m65/Z80_instr_shftrot_RRC.s
+1 -1
View File
@@ -18,7 +18,7 @@
!macro Z80_RRC_VIA_HL {
jsr (VEC_fetch_via_HL)
jsr (VEC_fetch_via_HL_back)
tax
ror
src/zvm_m65/Z80_instr_shftrot_SLA.s
+1 -1
View File
@@ -14,7 +14,7 @@
!macro Z80_SLA_VIA_HL {
jsr (VEC_fetch_via_HL)
jsr (VEC_fetch_via_HL_back)
asl
sta [PTR_DATA],z
src/zvm_m65/Z80_instr_shftrot_SLL.s
+1 -1
View File
@@ -15,7 +15,7 @@
!macro Z80_SLL_VIA_HL {
jsr (VEC_fetch_via_HL)
jsr (VEC_fetch_via_HL_back)
sec
rol
src/zvm_m65/Z80_instr_shftrot_SRA.s
+1 -1
View File
@@ -18,7 +18,7 @@
!macro Z80_SRA_VIA_HL {
jsr (VEC_fetch_via_HL)
jsr (VEC_fetch_via_HL_back)
tax
ror
src/zvm_m65/Z80_instr_shftrot_SRL.s
+1 -1
View File
@@ -15,7 +15,7 @@
!macro Z80_SRL_VIA_HL {
jsr (VEC_fetch_via_HL)
jsr (VEC_fetch_via_HL_back)
clc
ror
src/zvm_m65/z80_instr_bit.s
+16 -16
View File
@@ -872,49 +872,49 @@ Z80_instr_CB_FF: ; SET 7,A
Z80_instr_CB_C6: ; SET 0,(HL)
jsr (VEC_fetch_via_HL)
jsr (VEC_fetch_via_HL_back)
ora #%00000001
jmp ZVM_store_next
Z80_instr_CB_CE: ; SET 1,(HL)
jsr (VEC_fetch_via_HL)
jsr (VEC_fetch_via_HL_back)
ora #%00000010
jmp ZVM_store_next
Z80_instr_CB_D6: ; SET 2,(HL)
jsr (VEC_fetch_via_HL)
jsr (VEC_fetch_via_HL_back)
ora #%00000100
jmp ZVM_store_next
Z80_instr_CB_DE: ; SET 3,(HL)
jsr (VEC_fetch_via_HL)
jsr (VEC_fetch_via_HL_back)
ora #%00001000
jmp ZVM_store_next
Z80_instr_CB_E6: ; SET 4,(HL)
jsr (VEC_fetch_via_HL)
jsr (VEC_fetch_via_HL_back)
ora #%00010000
jmp ZVM_store_next
Z80_instr_CB_EE: ; SET 5,(HL)
jsr (VEC_fetch_via_HL)
jsr (VEC_fetch_via_HL_back)
ora #%00100000
jmp ZVM_store_next
Z80_instr_CB_F6: ; SET 6,(HL)
jsr (VEC_fetch_via_HL)
jsr (VEC_fetch_via_HL_back)
ora #%01000000
jmp ZVM_store_next
Z80_instr_CB_FE: ; SET 7,(HL)
jsr (VEC_fetch_via_HL)
jsr (VEC_fetch_via_HL_back)
ora #%10000000
jmp ZVM_store_next
@@ -1256,49 +1256,49 @@ Z80_instr_CB_BF: ; RES 7,A
Z80_instr_CB_86: ; RES 0,(HL)
jsr (VEC_fetch_via_HL)
jsr (VEC_fetch_via_HL_back)
and #%11111110
jmp ZVM_store_next
Z80_instr_CB_8E: ; RES 1,(HL)
jsr (VEC_fetch_via_HL)
jsr (VEC_fetch_via_HL_back)
and #%11111101
jmp ZVM_store_next
Z80_instr_CB_96: ; RES 2,(HL)
jsr (VEC_fetch_via_HL)
jsr (VEC_fetch_via_HL_back)
and #%11111011
jmp ZVM_store_next
Z80_instr_CB_9E: ; RES 3,(HL)
jsr (VEC_fetch_via_HL)
jsr (VEC_fetch_via_HL_back)
and #%11110111
jmp ZVM_store_next
Z80_instr_CB_A6: ; RES 4,(HL)
jsr (VEC_fetch_via_HL)
jsr (VEC_fetch_via_HL_back)
and #%11101111
jmp ZVM_store_next
Z80_instr_CB_AE: ; RES 5,(HL)
jsr (VEC_fetch_via_HL)
jsr (VEC_fetch_via_HL_back)
and #%11011111
jmp ZVM_store_next
Z80_instr_CB_B6: ; RES 6,(HL)
jsr (VEC_fetch_via_HL)
jsr (VEC_fetch_via_HL_back)
and #%10111111
jmp ZVM_store_next
Z80_instr_CB_BE: ; RES 7,(HL)
jsr (VEC_fetch_via_HL)
jsr (VEC_fetch_via_HL_back)
and #%01111111
jmp ZVM_store_next
src/zvm_m65/z80_instr_math_8bit.s
+2 -2
View File
@@ -612,7 +612,7 @@ Z80_common_INC:
Z80_instr_34: ; INC (HL)
jsr (VEC_fetch_via_HL)
jsr (VEC_fetch_via_HL_back)
tax
inc
sta [PTR_DATA],z
@@ -668,7 +668,7 @@ Z80_common_DEC:
Z80_instr_35: ; DEC (HL)
jsr (VEC_fetch_via_HL)
jsr (VEC_fetch_via_HL_back)
tax
dec
sta [PTR_DATA],z
src/zvm_m65/z80_instr_rotate_shift.s
+2 -2
View File
@@ -8,7 +8,7 @@
Z80_instr_ED_67: ; RRD
jsr (VEC_fetch_via_HL)
jsr (VEC_fetch_via_HL_back)
sta REG_TMP1
lda REG_A
@@ -47,7 +47,7 @@ Z80_instr_ED_67: ; RRD
Z80_instr_ED_6F: ; RLD
jsr (VEC_fetch_via_HL)
jsr (VEC_fetch_via_HL_back)
sta REG_TMP1
lda REG_A
src/zvm_m65/z80_reset.s
+38
View File
@@ -0,0 +1,38 @@
;
; Z80 CPU reset
;
Z80_reset:
; Reset registers and internal emulation data
lda #$00
tay
@1:
sta z80_cpustate__start, y
iny
cmp #(z80_cpustate__end - z80_cpustate__start + 1)
bne @1
dew REG_AF ; AF and SP have $FFFF value at start
dew REG_SP
lda TIME+2 ; give a little initial randomness to register R
sta REG_R06
; The engine requires all the Z80 visible memory to be present within the 1st 16MB,
; so set the most significant buytes of 32-bit pointers to 0.
stz REG_BC_EXT1+1
stz REG_DE_EXT1+1
stz REG_HL_EXT1+1
stz REG_SP_EXT1+1
stz REG_PC_EXT1+1
stz PTR_IXY_d_EXT1+1
stz PTR_DATA_EXT1+1
; Default bank is 1 (the fastest, continuous memory)
jmp ZVM_set_bank_1
src/zvm_m65/zvm_banking.s
+12 -3
View File
@@ -34,9 +34,18 @@ ZVM_set_bank_1:
; XXX use DMAgic to switch banks (vectors on zeropage)
lda #$04 ; all the Z80 bank 1 memory is located in $0004:$xxxx
sta PTR_DATA+2
sta PTR_IXY_d+2
; Since all the Z80 bank 1 memory is located in $0005:$xxxx,
; we can set some bytes in certain pointers for faster execution
lda #$05
sta REG_BC_EXT1+0
sta REG_DE_EXT1+0
sta REG_HL_EXT1+0
sta REG_SP_EXT1+0
sta REG_PC_EXT1+0
sta PTR_IXY_d_EXT1+0
sta PTR_DATA_EXT1+0
rts
src/zvm_m65/zvm_bios.s
+2 -21
View File
@@ -53,30 +53,11 @@ zvm_BIOS_00_BOOT: ; Cold start
; XXX !!!
; XXX fetch RAM disk image
; XXX fetch RAM disk image, CPM3.SYS, command interpreter
; XXX close all the files, reset I/O, set screen mode
; XXX clear memory
; Reset registers and internal emulation data
ldz #$00 ; .Z is required to be 0 all the time
lda #$00
tay
@1:
sta REG_AF, y
iny
cmp #(REG_IFF2+1)
bne @1
dew REG_AF ; AF and SP have $FFFF value on start
dew REG_SP
lda TIME+2 ; give a little initial randomness to register R
sta REG_R06
; XXX restore all *_EXT1 values
; XXX load CPM3.SYS
jsr Z80_reset
; FALLTROUGH